Quartus II software version 4.2 delivers the highest performance available for FPGAs and CPLDs. In addition to industry-leading performance, this software release introduces the PowerPlay power analysis and optimization technology. Version 4.2 of the Quartus II software includes a wide range of new features and technology enhancements.
Performance
Quartus II software version 4.2 delivers higher average performance for Altera FPGA and CPLD devices than Xilinx ISE software 6.3i SP1 delivers for similar category Xilinx devices. Benchmarks show an average of:
- 39% higher performance on Stratix® II devices when compared to Virtex-4 devices
- 60% higher performance on Cyclone™ II devices when compared to Spartan-3 devices
- 50% higher performance on MAX® II devices when compared to CoolRunner2 devices
PowerPlay Power Analysis & Optimization
PowerPlay technology allows you to accurately analyze and optimize both dynamic and static power consumption. Quartus II software version 4.2 features the new PowerPlay power analyzer, including detailed thermal dissipation reports that can be used to optimize designs for power. Automated Quartus II PowerPlay optimization features will be introduced in 2005.
Ease-of-Use
- Early Timing Estimate Fitter Option—Improves design iteration time by providing a rough preliminary timing estimate for a design in just a few minutes. Estimates are within 10-20 percent of the full compilation timing results.
- Soft LVDS Megafunction—Simplifies implementing LVDS communication with Cyclone II and Cyclone devices.
- Incremental Synthesis & 20 Percent Faster Run Times With Quartus II Integrated Synthesis—Incremental synthesis gives designers more control over design changes and improves synthesis run times. Other enhancements to the Quartus II integrated synthesis feature shorten average run times by 20 percent even when not using the incremental synthesis feature.
New SOPC Builder Features
- Clock Domain Crossing Circuitry—SOPC Builder can now automatically add specialized circuitry to support transactions between peripherals operating on different clocks.
- Component Editor—New feature to better support integrating customer user logic into SOPC Builder systems.
New Verification Features
- New Timing Analysis & Fitting Features—New features analyze and control clock skew, allow designers to model clock jitter, and enable better analysis and optimization of control signals.
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