Cadant Uses APEX 20KE Devices to Achieve Wire-Speed Processing in Cable Modem Termination System
As adoption of broadband cable services gains widespread implementation, the need to offer a broader, more reliable service arises. Key challenges in supporting broadband cable services are providing differentiated service, accommodating new users and new applications, and maintaining a reliable, high-performance service. To meet these challenges, the major cable system companies, referred to as multiple system operators (MSOs), have implemented a standard technical specification called the data over cable service interface specification (DOCSISTM 1.1), which increasingly requires quality of service (QoS) features and high-reliability, high-availability infrastructures, including new-generation cable modem termination systems (CMTSs).
In general, a feature-rich, QoS-enabled CMTS will provide for packet classification, packet prioritization, per-flow policing, congestion control, flow control, fine-grained queuing, scheduling, and per-flow traffic shaping. Hardware-assisted QoS processing (wire-speed processing) is generally required to perform these QoS functions without negatively impacting CMTS throughput. A CMTS design capable of wire-speed processing will be able to complete all of the QoS functions plus all of the functions associated with forwarding, counts, and measurements in less time than the shortest expected inter-packet arrival time. Without wire-speed processing, these functions can cause delay, forcing the CMTS to queue and delay processing, which in turn causes a lower grade of service, lower throughput, lower bandwidth, and less response. The consequent degradation in perceived performance will result in a loss of customer satisfaction.
Cadant, Inc., a leading supplier of carrier-class CMTSs, surpassed these broadband barriers by integrating Altera's APEX 20KE devices into their Cadant C4TM CMTS (see Figure 1). By implementing processing functions via programmable logic, Cadant avoided the long development times of using an ASIC and attained much greater speeds than with a pure software approach. Cadant found that the APEX 20KE device's architectural features, including high-speed I/O buffers, phase-locked loops (PLLs), and flexible embedded memory structures are especially advantageous for CMTS designs.
Figure 1. Cadant C4 CMTS
Cadant's Corporate Technology Officer, Tom Cloonan, said, "Altera's APEX devices provided the performance-intensive elements we needed to achieve the rigorous speed requirements of the DOCSIS 1.1 specification. Capabilities like True-LVDSTM circuitry and on-chip phase-locked loops (PLLs) were a great asset to the design of our C4 Cable Modem Termination System, which as a result offers the high-performance and high-availability features historically found only in true carrier systems such as Class 4 toll-switching equipment."
Using APEX 20KE for CMTS designs
Altera's APEX 20KE devices support a number of I/O standards and voltages. By allowing multiple I/O voltages, APEX 20KE devices can be used as interfaces between other components on the board, ranging from 1.8 V to 2.5 V and 3.3 V. More importantly, high-speed I/O options such as LVDS allow APEX 20KE devices to reach up to 840 Mbps per channel. These speeds can be achieved due to the on-chip PLLs, which perform clock multiplication for the serial-to-parallel converters.
By combining the PLLs and LVDS, a designer can increase the bandwidth of the system. For example, consider a switch fabric element with eight clients, two buses per client, eight I/Os per bus, and no LVDS-PLL combination. The total number of I/O pins is:
8 clients x 2 buses per client x 8 I/O pins per bus = 128 I/O pins
If the clock speed is given as 50 MHz, the total throughput is:
128 x 50 MHz = 6.4 Gpbs
Next, consider the system with the same system clock and the same number of clients with an LVDS-PLL combination. The total number of
I/O pins is:
8 clients x 4 buses per client x 2 I/O pins per bus = 64 I/O pins
64 I/O pins equals 32 LVDS pin pairs (which can be clocked at 8x the system clock by the PLLs), so the total throughput is:
32 LVDS pairs x 400 MHz = 25.6 Gbps
This result indicates that the LVDS-PLL combination results in a 4x throughput increase over the non-LVDS-PLL version of the switch fabric.
APEX 20KE devices feature on-chip memory that can be used in a number of CMTS-related functions, including FIFO buffers, RAM, ROM, and content-addressable memory (CAM). CAM is useful for symbolic compression and cache tagging. It can also be used in payload header suppression (PHS) to perform tree search algorithms that look up suppressed header patterns. When the size of the on-board CAM is inadequate, Altera can provide reference designs to help interface to larger, external CAM devices.
By combining the APEX 20KE device's on-board memory blocks with the clock multiplication capabilities of the PLLs, several useful DOCSIS-related functions can be created. For example, dual-clocked FIFOs can be used to store incoming Ethernet frames and convert them to 8- or 4-bit widths as necessary. A dual-port RAM combined with a PLL can provide clock domain transformation, where data is written to the RAM with one clock and read out with a multiplied version of the clock.
Finally, a PLL and a dual-port RAM can also perform data manipulation such as single-cycle read-modify writes, where a FIFO is written to at twice the rate it is read from. On every other write clock cycle, unmodified data is written to the FIFO, and on the other write clock cycles, the data is read out, modified with a mask value, and written back. In a DOCSIS-compliant CMTS, this function can be used to manipulate packet counts in one cycle, and with a high dress of memory utilization efficiency.
Conclusion
As the DOCSIS standard evolves in response to system improvements and changing customer demands, it becomes apparent that the ideal implementation for DOCSIS-compliant equipment has flexibility and high performance. A combination of programmable logic and a high-performance processor satisfies these requirements, allowing cable modem manufacturers such as Cadant, Inc. the option to easily modify their product designs and the products themselves, if needed, to meet changing conditions. The expected advances in programmable logic, including higher performance, more and faster I/O, increased memory, and greater density ensure the PLD's suitability for cable-modem network processing tasks. Additionally, Altera's Excalibur devices, which contain soft and hard embedded processor cores, will further the application of programmable logic to these tasks, allowing even greater integration and higher performance in the near future.
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