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For Release: March 18, 1999
Released by EIA - Electronic Industries Alliance
JEDEC Subcommittee Approves Standard Test and Programming Language
Arlington, VA--The JEDEC Solid State Technology Association's PLD committee, JC-42.1, today announced the completion of more than a year of work on the Standard Test and Programming Language (STAPL), formerly known as the Jam™ programming and test language. The committee passed a vote to send the language to the JEDEC Board of Directors for its final review process. Standardization will be final if the full JEDEC Board ratifies this proposal through a vote, which is expected to take place before mid-year.
STAPL is a vendor- and platform-independent language for programming and testing devices via the IEEE standard 1149.1 interface, commonly known as JTAG. STAPL enables programming of designs into programmable logic devices (PLDs) offered by a variety of PLD vendors. STAPL is also suitable for testing 1149.1-compliant devices.
"STAPL has been under review for over a year-and-a-half; the vote of this committee reflects its belief that STAPL is sufficiently powerful and efficient to provide significant benefits to developers using programmable logic," said Bryon Moyer, Subcommittee Chairman. "This belief is predicated on the fact that all the concerns of the committee were addressed by adding features and enhancements that satisfied the requirements of JTAG-programmable PLD manufacturers and tools vendors."
The STAPl language allows a user to create a STAPL-compliant programming or testing file as a part of the design process. This file can then be executed by any STAPL-compliant tool. This provides a universal language and toolset that addresses all PLDs and all programming methodologies.
A follow-up project to the STAPl specification will allow STAPL files to be compiled for lower-level implementation. Compilation can accelerate in-system programming by creating smaller file sizes and allowing shorter programming times. It also reduces the implementation memory requirements, making it particularly appropriate for embedded applications with limited resources.
JEDEC is the semiconductor engineering standardization body of the Electronics Industries Alliance (EIA), a national trade association representing U.S. manufacturers in all areas of the electronics industry for over 75 years. JEDEC has been the foremost standards development organization for the semiconductor industry since 1958.
JEDEC develops standards through its 11 Committees and 31 Subcommittees overseen by the JEDEC Board of Directors. Over 300 member companies representing every segment of the industry actively participate on these Committees to develop standards to meet the industry and user needs.
For more information about the Standard Test and Programming Language (STAPL), contact: Mr. Bryon Moyer, Altera Corporation, 101 Innovation Drive, San Jose, CA 95134 Tel: 408-544-6442, FAX: 408-544-6612, E-mail: bryon_moyer@altera.com
For more information about JEDEC and to access JEDEC standards online, visit the web site at http://www.jedec.org.
The Electronics Industries Alliance is a federation of associations and sectors operating the most competitive and innovative industry in existence. We are committed to promoting business opportunities for our industries. Comprised of over 2100 members, we represent 80% of the $550 billion U.S. electronics industry. Our member and sector associations represent telecommunications, consumer electronics, components, government electronics, semiconductor standards, as well as other vital areas of the U.S. electronics industry.
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