For Release: September 20, 1999
Altera Upgrades FIR Filter Compiler Design Solution
- Interpolation and Decimation Options Enable Better Performance and Lower-Power Filters to be Implemented in Altera PLDs
- Delivers Significant Performance and Cost Benefits over DSP Processors and Standard ASSPs
- Generates Simulation Models for VHDL, Verilog, and The MathWorks' MATLAB® and Simulink®
San Jose, Calif., September 20, 1999--Altera Corporation (Nasdaq: ALTR) today announced a new version of its FIR Filter Compiler, which adds Interpolation and Decimation functions to the easiest-to-use, most flexible FIR filter design tool in the programmable logic industry. The FIR Filter Compiler also includes a fixed point to floating point coefficient analyzer. Interpolation and Decimation, as well as the coefficient analyzer, are innovative features that are unique to the PLD industry. The FIR Filter Compiler still retains the performance optimization of the previous version, and delivers up to a 13x performance improvement and a 25x cost advantage over standard DSP processors.
"Altera's FIR Compiler has already proven that it offers significant performance and cost benefits when the design flow is compared to traditional DSP processors and standard ASSPs." said Craig Lytle, senior director of Altera's Intellectual Property Business Unit. "By upgrading the FIR Compiler with new features that are one-of-a-kind in the industry, Altera is continuing to dedicate itself to providing DSP designers with a PLD alternative for DSP applications."
Using seamlessly integrated design tools developed by Altera and The MathWorks, developers can quickly design, simulate, implement, and test systems that incorporate FIR filters. The FIR Filter Compiler can accelerate the system design process and improve time to market by up to 6 to 10 weeks.
Altera's FIR Filter Compiler is optimized for Altera's APEX™ and FLEX® PLD families and is ideal for use in data and wireless communications, digital cable and TV, instrumentation and mass storage applications.
New Features in FIR Filter Compiler
Interpolation and Decimation are widely used functions that change the effective sample rate of a signal. Decimation is typically used in receivers, and allows users to employ simpler and less-costly analog anti-aliasing filters. It also improves a system's signal-to-noise ratio. Interpolation is typically used in transmitters to increase the precision and signal-to-noise ratio of a system by adding points to the tranmitted digital data.
A new fixed point vs. floating point coefficient analyzer allows users to quickly evaluate quantization effects via a simple graphical user interface. This makes it easy for system designers to determine the necessary hardware precision.
"We needed a solution that allowed us to use our existing analog anti-aliasing filter to accelerate time to market. We determined that the Altera low-pass decimation FIR filter was the best solution, since the DSP processor cannot handle this function fast enough at the same time that it is performing other system functions," said Charlie Evans, a hardware engineer at Hewlett Packard Co. STD Division.
MegaWizard™ Plug-In Design Support
The FIR Compiler provides a complete system design environment, putting the user in control. The MegaWizard™ Plug-In, a parameterization tool which offer designers maximum flexibility in integrating complex logic cores into their designs, allows users to specify and verify parameters interactively at the system level, as well as implementation level. The user controls the number of taps, data bit-width, coefficient bit-width, sample frequency, output resolution, saturation, rounding, truncation, coefficient scaling, size/speed architecture optimization, and interpolation and decimation factors, as well as additional optimization based on symmetrical or anti-symmetrical properties of filters.
Availability & Pricing
The FIR Compiler (Ordering Code: PLSM-FIR) is available now for $4,995. Included with the megafunction is a complete User Guide.
Safe Harbor Notice
This press release contains "forward looking statements" which are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Forward looking statements are generally preceded by words such as "expects," "believes," "anticipates," "projects," or "intends." Investors are cautioned that all forward-looking statements in this release involve risks and uncertainty, including without limitation the risks that the Company's products will not satisfy customer demands, that other companies will develop products with higher densities than those offered by the Company, and that yields will not be sufficient to support projected pricing. Please refer to the Company's Securities and Exchange Commission filings, copies of which are available from the Company without charge, for further information.
About Altera
Altera Corporation, The Programmable Solutions Company™, was founded in 1983 and is a worldwide leader in high-performance, high-density programmable logic devices and associated computer aided engineering (CAE) logic development tools. Programmable logic devices are semiconductor chips that offer on-site programmability to customers. The chips are programmed using tools that run on personal computers or engineering work stations. User benefits include ease of use, lower risk, and fast time-to-market. The company offers the broadest line of CMOS programmable logic devices that address high-speed, high-density, and low-power applications. Altera products serve a broad range of markets, including telecommunications, data communications, computer peripherals, and industrial applications. Altera common stock is traded on the Nasdaq Stock Market under the symbol ALTR.
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