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For Release: November 1, 1999
Altera Ships First 0.18-Micron APEX 20KE for SOPC-Based Communications Design
- New On-Chip Architectural Features, such as CAM, LVDS, and PLLs, Support High-Performance Requirements of Next-Generation Communications Design
- Family Provides Performance at High-Densities While Offering Complete Software Support and a Full-Range of Communications IP Cores
- Capabilities Underscore Company's Commitment to System-on-a-Programmable-ChipTM Strategy
San Jose, Calif., November 1, 1999--Altera Corporation (Nasdaq: ALTR) today announced shipment of the EP20K400E, the first member of Altera's APEXTM 20KE family of programmable logic devices (PLDs) that targets the needs of next-generation communications designs requiring high-performance, single-chip solutions. The first member implements 400,000 gates (1 million maximum system gates) and is based on an advanced 0.18-micron, six-layer-metal, 1.8-V process and offers a number of new architectural and functional features. Included among these features are on-chip content-addressable memory (CAM), low-voltage differential signaling (LVDS), and phase locked loops (PLLs), enabling designers to create true System-on-a-Programmable-Chip (SOPC) silicon for leading-edge communications applications such as Layer 3 routers and switches, wideband CDMA baseband signal processing, and ATM cell processing and traffic management.
"The APEX 20KE is shipping at a time when communications system designers are evaluating their requirements to create next-generation, high-end products," said Cliff Tong, Altera vice president of product marketing. "For the first time designers are in a position to create truly integrated communications products by utilizing our IP offerings, an APEX 20KE programmable logic device and Quartus™ development tools." According to Tong, Altera offers over 130 IP cores, in areas such as communications, bus interfaces, DSP, processors and peripherals, amassed through internal development and through its Altera Megafunctions Partners Program (AMPPSM) partners, comprising the programmable logic industry's most comprehensive IP selection.
About the APEX 20KE Family
The APEX 20KE family covers a density range from 60,000 gates (160,000 maximum system gates) up to 1.5 million gates (2.5 million maximum system gates) and offers system performance exceeding 160 MHz. All devices in the APEX 20KE family feature Altera's unique MultiCoreTM architecture, which combines LUT-based logic and product-term logic with embedded memory. The MultiCore architecture consists of large blocks called MegaLABTM structures, each of which is connected via Altera's continuous FastTrack® interconnect routing structure. Each embedded system block (ESB) within a MegaLAB structure contains 2,048 programmable bits that can be configured to support product-terms, dual-port RAM, ROM, or CAM.
CAM, a memory technology developed from RAM, accelerates applications such as network switching, packet routing, and pattern recognition that require fast searches of databases, lists, and patterns. CAM simultaneously compares input data against an entire list of pre-stored entries in a single clock cycle, thereby enabling a significant reduction in search time. Embedded CAM support in APEX 20KE family represents a first for the programmable logic industry.
Altera's APEX 20KE family also has support for up to four PLLs, two of which support the LVDS standard with data rates of up to 622 Mbits/s, allowing for 20 Gbps bandwidth. This new data interface standard provides significant advantages for many different applications, such as imaging systems, LAN stackable hubs, and telecommunication switches. When high-bandwidth communication is required, LVDS provides a robust high-speed and low-power interface solution with improved noise immunity.
High I/O performance is further enhanced by support for advanced I/O standards including GTL+, SSTL-3, SSTL-2, AGP, CTT, LVTTL and LVCMOS, as well as full 64-bit, 66-MHz PCI compliance. These high-bandwidth I/O standards allow for flexible high-performance interfacing with back planes, processors, high-speed memories, and graphic ports. In addition, the presence of eight independent I/O blocks allows for multiple I/O standards and multiple I/O voltages to be used at once.
The APEX 20KE enhanced PLLs provide a number of features targeted at enhancing device and system-level performance. The ClockLockTM function reduces clock delay and skew to improve I/O performance up to 35 percent. The ClockBoostTM feature provides for flexible multiplication by a wide range of factors over the widest frequency range in the PLD industry, significantly increasing datapath bandwidth and reducing the use of logic resources. The ClockShiftTM feature allows a clock signal to be shifted in time or in phase and, in combination with the ability to drive the PLL output off-chip, can be used to remove board delay.
In addition to traditional QFP and 1.27-mm pitch BGA packages, Altera's APEX 20KE family will be offered in FineLine BGATM packages and will support the SameFrameTM feature. This capability allows designers to migrate between FineLine BGA packages of different pin counts without having to perform board re-layout, thus providing a new level of package migration flexibility.
About EP20K400E Device
The EP20K400E is the first member of the APEX 20KE family of System-on-a-Programmable-Chip devices. The EP20K400E device features 16,640 logic elements (LEs) and 212,992 RAM bits in embedded blocks, which can be configured as 1,664 macrocells. The high-performance EP20K400E PLD has 400,000 typical gates (1 million maximum system gates), up to 488 maximum user I/O pins, and interfaces at 1.8-, 2.5-, and 3.3-volts using MultiVoltTM I/O support.
Design Tools
APEX 20KE devices are supported by Quartus, Altera's fourth-generation development environment. The Quartus software was developed to support system-level designs and features good-as-native links to industry-leading third-party tools from Exemplar Logic, Model Technology, Synopsys, Synplicity, Viewlogic, and other leading EDA vendors. In addition, designers will be able to use the SignalTapTM logic analysis tool for in-system hardware debugging.
The Quartus software supports major operating systems, including Windows NT version 4.0, Windows 98 on PCs, the Solaris 2.6 operating system on Sun SPARCstations, and the HP-UX operating system. Annual subscription for the Altera Development tools is $2,000 for a node-locked PC license, which includes full-featured Quartus and MAX+PLUS® II development software and 12 months of software upgrades.
Efficient IP Integration
By implementing intellectual property (IP) as easy-to-use parameterized cores, designers can reduce overall design time and focus more of their efforts on value-added parts of the system. Altera offers this IP in the form of Altera-developed MegaCoreTM megafunctions and optimized cores from third-party AMPP members. Altera MegaCore megafunctions and AMPP cores include PCI and other bus interfaces, processors and peripherals, DSP cores, and communications functions. Altera's Quartus design environment simplifies IP integration through its OpenCoreTM test-drive feature and MegaWizardTM Plug-In Manager.
Availability, Packaging, & Pricing
The EP20K400E is offered in a 652-pin BGA package and 672-pin FineLine BGA package. Projected volume pricing by mid-year 2000 starts at $125.
Safe Harbor Notice
This press release contains "forward looking statements" which are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Forward looking statements are generally preceded by words such as "expects," "believes," "anticipates," "projects," or "intends." Investors are cautioned that all forward-looking statements in this release involve risks and uncertainty, including without limitation the risks that the Company's products will not satisfy customer demands, that other companies will develop products with higher densities than those offered by the Company, and that yields will not be sufficient to support projected pricing. Please refer to the Company's Securities and Exchange Commission filings, copies of which are available from the Company without charge, for further information.
About Altera Corporation
Altera Corporation, The Programmable Solutions Company™, was founded in 1983 and is a leading supplier of programmable logic devices and associated logic development software tools. Programmable logic devices are semiconductor chips that can be programmed on-site, using software tools that run on personal computers or engineering workstations. User benefits include ease of use, lower risk, and fast time-to-market. Altera's CMOS-based programmable logic devices address high-speed, high-density and low-power applications in the telecommunications, data communications, computer peripheral, and industrial markets. Altera common stock is traded on the Nasdaq Stock Market under the symbol ALTR. A photograph can be located at http://www.businesswire.com/altera.
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