For Release: March 12, 2002
Altera Certified IP Cores for SOPC Builder Available Now
Portfolio of SOPC Builder-Ready Intellectual Property Cores Available Today for Altera's Excalibur Embedded Processor Solutions
San Jose, Calif., March 12, 2002 -- Altera Corporation (Nasdaq: ALTR) today announced the immediate availability of intellectual property (IP) cores certified 'SOPC Builder-Ready,' providing seamless connectivity to Altera's Excalibur™ embedded processor solutions. Optimized for use with the recently announced SOPC Builder system development tool, these cores include software components such as device drivers, configuration files, board support packages (BSP), test code and simulation models that support software development for the Nios™ soft core processor and ARM®-based Excalibur devices.
SOPC Builder-Ready IP cores are available now from both Altera and Altera Megafunction Partners Program (AMPPSM) members for system-on-a-programmable-chip (SOPC) designs. Designers can also integrate their own IP into the SOPC Builder design flow.
SOPC Builder simplifies and accelerates the development of embedded systems in Altera's programmable logic devices (PLDs). Combined with SOPC Builder-Ready IP, this powerful solution allows designers to go from concept to system in minutes by automating the task of connecting blocks of IP such as processor, memory, communications, bus interface and DSP cores to create a custom SOPC.
"For years, system designers have been manually connecting IP peripheral functions to embedded processors, taking anywhere from weeks to months to accomplish," said Justin Cowling, Altera's intellectual property marketing director. "With SOPC Builder and SOPC Builder-Ready IP, designers can now define, parameterize and link IP cores automatically to create a custom system-on-a-programmable-chip in minutes. Altera currently has more than 200 IP cores available for integration with the Excalibur embedded processor solutions and will continue adding cores to its library of SOPC Builder-Ready certified IP."
The SOPC Builder tool was designed from the ground up to integrate Altera and third-party IP and the ARM-based Excalibur or Nios processors. The SOPC Builder-Ready IP certification is part of Altera's strategy of combining system integration tools with plug-in IP for embedded processor, digital signal processing (DSP) and communication systems designs.
SOPC Builder-Ready IP cores include on-chip bus interfaces, configuration files and C code routines that may be used to perform initialization and read/write transactions with the on-chip processor. Designers can easily configure master, slave, or direct memory access (DMA) on-chip connections and parameters within SOPC Builder's intuitive graphical user interface (GUI).
With the OpenCore® evaluation feature, designers can test drive IP cores for free in the Quartus® II development software. Many cores also support OpenCore Plus, which enables free hardware evaluation and RTL-level simulation prior to purchasing a license.
The following SOPC Builder-Ready IP cores are available now:
| Core |
SOPC Builder Bus Interface(s) |
Vendor |
|
Nios Embedded Processor, including
- Interrupt Controller
- Custom Instruction Interface
- On-chip Debugging Core
- Configurable Multiply Unit
|
Avalon |
Altera Corporation |
| UART |
Avalon |
Altera Corporation |
| SPI |
Avalon |
Altera Corporation |
| DMA |
Avalon |
Altera Corporation |
| SDRAM Controller |
Avalon |
Altera Corporation |
| SSRAM I/F |
Avalon |
Altera Corporation |
| SRAM / Flash / ROM I/F |
Avalon |
Altera Corporation |
| On-Chip SRAM |
Avalon |
Altera Corporation |
| On-Chip ROM |
Avalon |
Altera Corporation |
| General-Purpose Timer |
Avalon |
Altera Corporation |
| Watchdog Timer |
Avalon |
Altera Corporation |
| PIO |
Avalon |
Altera Corporation |
| Interface to User Logic |
Avalon |
Altera Corporation |
| PCI32 Nios Target |
Avalon |
Altera Corporation |
ARM922T™ Stripe, including Hard IP:
- Interrupt Controller
- General-Purpose Timer
- Watchdog Timer
- SDRAM Controller (SDR & DDR)
- Bus Expansion (EBI)
- UART
- AHB Bridge
- Configuration Logic Master
- PLD-to-Stripe Bridge
- Stripe-to-PLD Bridge
- SRAM (Single and Dual port)
|
AHB |
Altera Corporation |
| 10/100 Ethernet MAC |
AHB |
Altera Corporation |
| UART with FIFO Buffer |
AHB |
Altera Corporation |
| Nios-PCI Bridge |
Avalon |
PLDApplications |
| AMBA-PCI Bridge |
AHB |
PLDApplications |
| USB 2.0 High/Full Speed Core Controller |
Avalon/AHB |
Mentor Graphics - Inventra |
| USB 1.1 Full Speed Core Controller |
Avalon/AHB |
Mentor Graphics - Inventra |
| CAN 2.0 Network Controller |
Avalon/AHB |
Mentor Graphics - Inventra |
| M16550S Enhanced UART |
Avalon/AHB |
Mentor Graphics - Inventra |
| ARM Master |
AHB |
Eureka Technology |
| ARM Slave |
AHB |
Eureka Technology |
| ARM Dual UART |
AHB |
Eureka Technology |
| ARM DMA |
AHB |
Eureka Technology |
| ARM-to-PCI Host Bridge |
AHB |
Eureka Technology |
About the Altera Megafunction Partners Program (AMPP)
The Altera Megafunction Partners Program, established in August 1995, was created to bring the advantages of design reuse to users of Altera PLDs. AMPP is an alliance between Altera and developers of IP cores that encourages megafunction development. Altera provides technical information and training to the AMPP partners, who create and support IP cores targeted for Altera PLDs. Currently, there are over 30 AMPP partners who offer more than 150 megafunctions. Customers may request a free evaluation of any of these cores through Altera's megafunction listings at http://www.altera.com/ipmegastore.
About Altera
Altera Corporation (Nasdaq: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at http://www.altera.com.
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