Release Notes For ModelSim Altera 6.5e Feb 26 2010 Copyright 1991-2010 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. The use herein of a third-party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. The following are trademarks of of Mentor Graphics Corporation: Questa, ModelSim, JobSpy, and Signal Spy. A current list of Mentor Graphics trademarks may be viewed at www.mentor.com/terms_conditions/trademarks.cfm. End-User License Agreement: You can print a copy of the End-User License Agreement from: www.mentor.com/terms_conditions/enduser.cfm. ______________________________________________________________________ Product Installation and Licensing Information For brief instructions about product installation please visit the "install_notes" file in www.model.com. The install_notes file can be viewed at: [1]http://www.model.com/products/release.asp For detailed information about product installation and licensing see the ModelSim Start Here Guide. The manual can be downloaded from: [2]http://www.model.com/support/documentation.asp Release Notes Archives For release notes of previous versions visit the release notes archive at: [3]http://www.model.com/support/default.asp or find them in the installed modeltech tree in /docs/rlsnotes How to get Support ModelSim Altera is supported by Altera Corporation * World-Wide-Web Support [4]http://www.altera.com/mySupport ______________________________________________________________________ Index to Release Notes [5]Key Information [6]User Interface Defects Repaired in 6.5e [7]Verilog Defects Repaired in 6.5e [8]PLI Defects Repaired in 6.5e [9]VHDL Defects Repaired in 6.5e [10]FLI Defects Repaired in 6.5e [11]VITAL Defects Repaired in 6.5e [12]SystemC Defects Repaired in 6.5e [13]Assertion Defects Repaired in 6.5e [14]Mixed Language Defects Repaired in 6.5e [15]Coverage Defects Repaired in 6.5e [16]General Defects Repaired in 6.5e [17]Mentor Graphics DRs Repaired in 6.5e [18]Known Defects in 6.5e [19]Product Changes to 6.5e [20]New Features Added to 6.5e ______________________________________________________________________ Key Information * The following lists the supported platforms: + win32aloem - Windows XP, Vista + sunos5aloem - Solaris 8, 9, 10 + linuxaloem - RedHat 9 and higher, RedHat Enterprise Linux 3, 4 and 5, SUSE Linux Enterprise Server 9.0, 9.1 and 10. ______________________________________________________________________ User Interface Defects Repaired in 6.5e * Using the Find function (clicking on the Binoculars button) from the Covergroups window resulted in a Tcl error. Find in the Covergroups window now works as expected. * SystemC enums will now display in symbolic (ASCII) form by default. They may be shown numerically by using radix -enumnumeric or by using the -radixenumnumeric flag allowed by many commands. When shown numerically, enums are formatted according to the current radix setting. This change follows the convention established for Verilog and SystemVerilog enums. * vmap will give an error if the MODELSIM environment variable is set and is not pointing to a modelsim.ini file. * The ability to filter out and show only those covergroup bins with zero coverage was broken. After selecting "Zero coverage only" in the filter dialog, the window was blank. This has been fixed. * Using the File > Print menu on the Windows platform could cause Tcl errors if the Dataflow or Schematic windows were active. This has been fixed. * The ability to filter the Covergroups window using the "Range" selection from the Filter Dialog often resulted in Tcl errors. This has been fixed. * During long simulation runs, or during very long debug sessions, the U/I can become slow or unresponsive. This issue has been resolved. * The Wave window horizontal scroll bar misbehaves when the time range is very large. This issue has been resolved. * Scrolling during drag and drop operations in the Wave window caused unnecessary repainting of the waveforms. This issue has been fixed. * In some cases Expression Builder failed to insert required white spaces to construct parsable expressions. This issue has been fixed. * The transcript sizelimit option only works in limited situations. This issue has been resolved. * The "c" key in the Dataflow window's Wave window did not correctly center on the current cursor after zooming in. * A Tcl error would occur if user tried to copy a part of a waveform using the Wave Editor menu. This issue is now fixed. * Changes to the default layout "Coverage" would not be saved across sessions. The issue was specific just to the "Coverage" layout, and it has been fixed. * Setting PrefWave(OpenLogAutoAddWave) to "0" still loads signals in Wave window. This issue is now fixed. * The value column in Locals window gets corrupted when resized for very long values. This issue has been fixed. * If "restart" is executed to reload a modified design, any opened FSM Viewer windows would not have their content updated to reflect the design changes. This problem has been fixed. * Errors would occur when trying to create or rename a group in the Wave window to the same name as a pre-existing group. * Certain SystemVerilog constructs were not handled properly by the Classgraph window. In particular, an array of classes could cause the Classgraph window to hang. These constructs are now handled properly. * After editing a file shown in the Source window, it was possible that vertical scrolling would become erratic. This has been fixed. * Group signals in the Wave window were not printable. This issue is now fixed. * PSL assertions did not appear in GUI. This issue is now fixed. * It was possible for a Tcl error to occur when using the Dataflow. The error would refer to the following: # invalid command name "_unbusyCusror" This problem has been fixed. * A new preference variable PrefSource(OpenOnStep) has been added to control opening the Source window during single stepping. * Under certain circumstances the name portion of the Wave window would not repond to scrolling, while the wave portion would scroll properly. This issue appeared primarly on the Windows platform, and has been fixed. * SystemVerilog Queues and other dynamic objects did not correctly update in the Objects window. * Files created by vcd2wlf were very slow to display in the Wave window. The problem was the files were being created without indexing data. The problem has been fixed. * If a large design was run for a while without logging and then the design was logged and run, the resulting WLF file could draw slowly or display strangely near the starting time. The problems have been resolved. * The View -> Verification Management --> Tracker menu item has been disabled (grayed out) for ModelSim-DE, since its functionality is not licensed in that product. * The Expanded Time background color variables have been renamed from waveBackground3 and waveBackground4 to the more meaningful names waveDeltaBackground and waveEventBackground. They now match the names described in the User's Manual. * The "Configure Directive..." item in the popup menu in the Cover Directives window resulted in an error when right-clicked over anything other than the cover directive itself. This has been fixed. * In the Cover Directives window, there was no way to set the value of "Limit" in the "Configure selected cover directives" dialog box back to the default value of "unlimited". This problem has been fixed. * In some instances, an expand box ("+") was drawn next to tree items in the Missed Toggles, Library, and Cover Directives window. When clicked, the expand box would disappear. This has been fixed. In those instances, the expand box will not be (incorrectly) drawn in the first place. * When viewing a large optimized wave display, some signals were missing transitions when the display was zoomed out. The issue has been fixed. ______________________________________________________________________ Verilog Defects Repaired in 6.5e * Sensitivity lists containing multiple arrayed events would not trigger properly in all cases. * In previous versions, error #8209 would be reported, but simulation would continue. Simulation now halts when this occurs. * $rtoi() may sometimes return an incorrect integer value for very large real input numbers. This issue has been fixed. * Verilog macros may contain an undef followed by a refdefinition. * Instantiations below a generate block would not use the correct liblist if the liblist was specified in a Verilog configuration instance clause for a parent instance. * Fixed a vlog crash that would occur when the 'inside' operator is specified in a case where the RHS is a parameterized queue. * vlog was incorrectly printing a 'no return' warning for 'extern' function prototypes declared in interfaces. * The evaluation of an "optimized" bit-wise binary operator incorrectly short-circuited the evaluation of operands that have side effects (an assignment expression, for example). * In some cases, calls to randomize() with an inline constraint would generate errors like: # ** Error: test.sv(12): Invalid call to class::randomize() via null class reference. even though the class handle was non-null. * Fixed crash during gate-level Verilog simulation when timing check violates. * Verilog macros containing `ifdef-`elsif-`endif constructs would fail to compile. * Indexing an unpacked array would cause large amounts of stack space to be used when running the simulation. We have addressed this problem for many cases. * False matches during SDF annotation when conditions arguments are specified in $setuphold and $recrem timing checks and the cell is not optimized. * vopt failed to resolve a relative hierarchical path when the first name in the path was a generate block and the generate block was declared higher up in the instance hierarchy. * ModelSim DE may issue the following spurious warning while compiling function calls: (vlog-2254) SystemVerilog testbench feature (randomization or coverage) detected in the design. These features are only supported in Questasim. This problem is now fixed. * Warnings are now issued for illegal access to local and protected data members within a parameterized class. * If an interface-port was left unconnected, vopt could crash when attempting to print an error message. * The error message, "(vsim-8285) Illegal concatenation of unpacked value." was printed without a line number. The line # is now indicated. * In some cases where fork..join_none processes were nested inside several layers of fork..join/join_any blocks, the outer processes would fail to complete after disabling some of the inner processes. * Using $init_signal_spy to mirror the value of a Verilog packed vector to an element of an unpacked array of a packed vector of the same size would result in an incorrect length mismatch error in vsim. This has been fixed. * The tcheck_set command didn't work with $recrem in the following scenario. The $recrem has a timecheck condtion but no timestamp condition. The customer uses tcheck_status on an instance to display all the timing checks. Then the SDF style string for RECOVERY part of $recrem is used with tcheck_set command that failed to find the specified timing check. * When a module that is in a protected region drove the source port of an output-to-output INTERCONNECT delay and -voptargs=+acc (or -pli) was specified on vsim command line, there was an annotation warning: This was really an error because the INTERCONNECT delay annotation did not happen. Fixed so that the source port in the protected region is found and the INTERCONNECT delays are annotated. * Error and rejection pathpulse behavior did not work correctly, for optimized gate-level cells, when there were multiple pending output schedules. ______________________________________________________________________ PLI Defects Repaired in 6.5e * When the vsim -tab switch was used to specify a tabfile for PLI registration, the tabfile information was lost after a restart command was issued, resulting in PLI initialization errors. This has been fixed. * When a VPI value-change callback is created for a multi-dimensional array, and multiple elements of the array are written at once (for example, by a continuous assignment), the callback may report an incorrect array index. ______________________________________________________________________ VHDL Defects Repaired in 6.5e * A crash would occur in a unoptimized design which instantiates a VHDL configuration whose entity is black boxed. * Under some circumstances, a subprogram that used an alias to another subprogram as a local declaration caused an internal error during compilation with -novopt or during optimization with vopt. * The simulator would report the following fatal error when loading a design: ** Error: (vsim-3171) Could not find machine code for '...'. No such file or directory. (errno = ENOENT) Load interrupted Error loading design This error was caused by incorrect code generation by vopt when a design contained a recursive instantiation of a design unit, and the recursive instantiation statement occurred within at least two levels of generate blocks. * Under some circumstances, a signal of a character-sized array type with user-defined resolution, used in the condition expression of an if statement, produced an internal error with vcom -novopt or optimization with vopt. This occurred in a process that only contained a single if statement where the reference to this signal was in the if condition clause or one of the elseif condition clauses. * Record signals which are composed of resolved composite fields and non-resolved composite fields could cause memory corruption and crashes. The same process needed to drive resolved composite fields and non-resolved composite fields from separate statements. * vcom, vopt, or vsim could crash if the longest static name of a signal being driven contained an index of a slice. This could occur if the actual to a formal signal parameter is a slice and the formal is indexed. * A formal parameter of a subprogram having the same name as a protected type method, when both the protected type and the subprogram were declared in the same declarative part, and when the subprogram was declared after the close of the protected type declaration (thus not being directly related), would cause the compiler to issue a duplicate declaration error (message #1294) when in fact such VHDL code is legal. This has been fixed, such code now compiles as legal code. * If an array types is not unconstrained, range checks for indexing operations were not done in some cases. If the index was out of range this could results in a crash with no useful information. The check is now performed and an error reported that the index is out of range. * If a breakpoint is place in the reset condition of an optimized process and is triggered incorrect simulation results will occur. The flip-flop process will behave as if the reset condition is FALSE even though it is TRUE. * The second occurrence of a function call could be ignored and the result of the previous call used. This would happen if the function calls had the same or equivalent arguments and one or more of the arguments was an array index expression where the index expression is not a constant. The option -nofunctionalias can be used on vopt to work around this issue. * A VHDL concurrent assertion statement whose condition contained an edge of a signal attribute or similar complex conditions caused a crash at runtime when the condition was evaluated. A specific example of this is the condition "rising_edge(clock'delayed(time))". * Message #151, which relates to integer overflow in accelerated versions of functions to_integer[unsigned return natural] and to_integer[signed return integer] in packages ieee.numeric_std and ieee.numeric_bit, could have its severity level changed (For example: via -fatal and -error) but this change would be ignored if the modelsim.ini file variable NumericStdNWarnings was set. This has been fixed. * vopt would fail with the message: # ** Error: Internal error: EXPR, val = 639, ../../../src/vcom/vh_print_expr.c(1306) If a component configuration or component specification had an attribute on a type. * If a package contains a vector signal and an entity/architecture that is being in-lined assigns to or waits on part of this package signal, a crash during elaboration could occur. * The instantiation of a component with an unconnected output port could be bound to the wrong entity by the default binding rule in the non-vopt flow. This happened when the candidate entity was missing only that particular port. ______________________________________________________________________ FLI Defects Repaired in 6.5e * The mti_Cmd() call would hang when processing commands with unbalanced "}" characters in them. ______________________________________________________________________ VITAL Defects Repaired in 6.5e ______________________________________________________________________ SystemC Defects Repaired in 6.5e * Fixed a crash during restart when a DPI import function is defined in a SystemC shared library. * sccom issuing undebuggable objects warnings during compilation of an unrelated file has been fixed. * sccom signal trapping (Ctrl-C) issue is fixed. ______________________________________________________________________ Assertion Defects Repaired in 6.5e ______________________________________________________________________ Mixed Language Defects Repaired in 6.5e * Fixed a mixed language (SystemVerilog/VHDL) elaboration issue that leads to DPI failures (i.e. (vsim-7014) The same DPI c_identifier ...was used for more than one export task or function in scope ... ). * $init_signal_spy would not initialize it's value when the source object was of VHDL real datatype and destination was of SystemVerilog real type. This has been fixed. * vopt would crash with a signal 11 if a lower level VHDL instance is bound to a Verilog module and the "architecture" fast is located in the same library as the design root. * A crash could occur in a VHDL design instantiating Verilog cells when the Verilog cells had cell optimizations and internally unused ports. * An instance clause in a Verilog configuration instantiated from a VHDL design would have no effect if the clause specified a path passing through a for-generate block. * vopt would produce an incorrect error message when a VHDL generic of type 'bit' was used to override an untyped Verilog parameter, with an initial value that could be folded to an integer. This has been fixed. * Using $init_signal_spy to mirror the value of an integer type to an element of an unpacked array of integers would result in a type mismatch error in vsim. This has been fixed. * vopt would produce an incorrect error message when a VHDL generic of type 'bit' was used to override a Verilog parameter of type 1-dimentional 1-bit packed vector, having an initial value that could be folded to an integer. This has been fixed. * Using elements of fields of records as actuals while binding to VHDL target scopes using SV bind construct would result in an incorrect error message in vsim. The error message was valid, but its text has been fixed to make it more clear to the user. * Using integer constants as actuals while binding to VHDL target scopes using SV bind construct would result in an incorrect error when vsim was invoked with -novopt option. This has been fixed. * Using parameters having initial values as strings with characters '\"' in them would make the Verilog module unusable at the SV-VHDL language boundaries in the vopt flow. This has been fixed. * Binding to invalid VHDL target scopes using the SV bind construct would sometimes not produce an error message when vsim was invoked with -novopt option. Such bind statements would result in binding to wrong VHDL targets. This has been fixed and now vsim will report a valid error message for such scenarios. * Using $init_signal_spy or $init_signal_driver with a Verilog packed bit vector of size more than 32 bits as the destination object would result in incorrect value being mirrored/driven. This has been fixed. * Annotating a large number of SDF files (close to the system limit of maximum number of file descriptors per process) caused annotation failures and subsequent elaboration failures too. This happened only when the SDF files were compiled (which is the default flow from 6.4 onwards). * When SDF annotation related errors were downgraded using "-warning" switch of vsim, the simulation still errored out. * A Verilog input port connected internally to a tran primitive and connected externally to a VHDL signal produced incorrect results in some cases. ______________________________________________________________________ Coverage Defects Repaired in 6.5e * We had a problem that when a *.ucdb file was opened in vsim -viewcov mode, the name of the dataset was truncated. This issue has been fixed. * Problem causing an internal error "Invalid TESTVECTOR attribute for ..." has been fixed. * The transition '1->0' would sometimes not be counted correctly when the concerned toggle node was added using toggle add -full command. This has been fixed. * The vcover report command now shows MAX_INT hits as "INF". * vcover merge was producing wrong warning message 6821 for assertion objects. * The coverage report command on a design unit was crashing when -total option was used. * xml2ucdb generated a segmentation fault for some cases because the parent XML file's format was not correctly inherited by it's child. This is now fixed. * xml2ucdb will return "0" only if everything is fine and there are no errors or warnings, and will return "1" in case any error(s) and/or warning(s) occured but the output UCDB was generated, and will return "2" in case the output UCDB was not generated. * The All False Branch was missing in details coverage text report for a long simulation run. * Current exclusions window would sometimes not show the exclusion set using a fine grained coverage pragma to turn off branch coverage for selected case statements. This has been fixed. ______________________________________________________________________ General Defects Repaired in 6.5e * Certain types of designs characterized by relatively flat netlists with many (10K+) instances in any particular region of the design, which had SDF being applied on those instances, would exhibit very long design load times because of an inefficiency in the way the SDF was applied. The design load time for this type of design has been improved. * Compiling PSL code into a library created with vlib -archive would result in a crash of the compiler. * Multiple restarts while logging SV string variables could result in an intermittent crash. ______________________________________________________________________ Mentor Graphics DRs Repaired in 6.5e * dts0100546674 - sccom issues duplicate undebuggable object warnings. * dts0100560622 - Abnormal exit on load with SDF. * dts0100606903 - FSM viewer is not updated after restart. * dts0100621312 - Simulator crash when loading optimized code. * dts0100623902 - vsim error #8209 should halt simulation. * dts0100629551 - Unexpected signal 11 error when compiling. * dts0100630194 - Values column in locals window gets corrupted on resize. * dts0100632847 - Custom layout is not used when configuring layout using Layout->Configure > when a design is loaded with coverage enabled. * dts0100636073 - Certain event triggers not functioning. * dts0100636182 - Unexpected error 3171. * dts0100636723 - vsim loads signal in the Wave window even if OpenLogAutoAddWave is set to '0'. * dts0100637502 - Crash while compiling VHDL93 code. * dts0100640194 - Extern function (in interface) warning message: Function has no return value assignment even though the function has a return value. * dts0100642634 - Dataflow window zoom fails. * dts0100643886 - "-tab" file list lost after restart. * dts0100646623 - Crash during gate-level Verilog simulation when timing check violates. * dts0100418548 - Wave window, drag and drop signals --> useless repainting. * dts0100614432 - Expression Builder: parser is unable to recognize the expression. * dts0100642120 - The "transcript sizelimit" command doesn't work in batch mode. * dts0100597528 - Waveform copy error. * dts0100642958 - Wave group errors. * dts0100590874 - Memory is not found in config liblist. * dts0100587097 - Verilog config does not bind correctly through a generate block. * dts0100615905 - Excessive stack allocation for expression temps. * dts0100651213 - Problem with drivers of record signal with resolved composite subelements and some subelements that are not resolved composites. * dts0100637464 - Invalid DPI load error: The same DPI c_identifier was used for more then one export task. * dts0100636938 - Problem with VHDL real to SystemVerilog real mapping during initialization. * dts0100646298 - 6.5 Only, "Invalid TESTVECTOR attribute for ..." error message from ranktest. * dts0100631913 - Toggle add -full misses transition. ______________________________________________________________________ Known Defects in 6.5e * On Windows platform, If Destructor breakpoint on SystemC object is set via command "bp -c < function_name >", Debugger sometimes does not stop at the breakpoint. * On Windows platform, if breakpoint is set on a SystemC object destructor, Debugger sometimes crashes while quitting simulation. This crash can be avoided by setting env variable SC_NO_LIB_UNLOAD, which will prevent unloading of the shared library. * The simulator will hang if it tries to create a WLF file while running on a Linux 64-bit operating system from a working directory which does not support large files. One common instance of this is executing an add wave command, when the working directory was created under an older 32-bit Linux OS. This is a Linux operating system bug and cannot be fixed by the simulator. A workaround for release 6.3 and above is to execute the simulator with command line option -wlfnolock. * The stack unwinder on the linux_x86_64 OS is unreliable. The unwinder is the fundamental facility provided by the OS for sampling where program execution is at. The unwinder is necessary for gathering performance data. This is a known issue with this specific OS and is why performance data will be incorrect or non-existent on this platform. * Users should be mindful of enabling both performance profiling and memory profiling at the same time. Memory profiling requires much overhead process, and it can skew the results of the performance profiling data. * On certain (RedHat) Linux Operating System versions the "-restore" feature occasionally fails. This is due to the memory allocation security (anti-hacking) feature of Linux. RedHat Enterprise release v.3 update3 was the first version to have this security feature. In these Linux releases two consecutive program invocations do not get the same memory allocation foot-print. For the "-restore" feature the simulator relies on having the same memory allocation foot-print. Users are advised to re-try this feature a few times as on average 3 out of 5 attempts are successful. In recent Linux versions, an override for this anti-hacking feature is provided. Please use it at your own discretion. * Support of debugging C code during a quit command was disabled on Windows. The corresponding C Debug command cdbg stop_on_quit was also disabled on Windows. * Specparams can be learned during the learn flow, but cannot be found on consumption. The workaround is to use full +acc deoptimization. * On Red Hat Enterprise Linux release 5 platform, If SIGSEGV signal occurs during the simulation and if CDEBUG is on, C-debugger traps the signal, and when continued, vsim gets terminated right away, instead of exiting with proper error status. * Code coverage is now giving results for SystemVerilog nested modules, interfaces and program blocks. One remaining issue is that if a nested module has more than one instance, only one of the instances will show code coverage data, and the data therein will be the sum of all the instances of that module. This will be improved in a later release. * The vpiPorts iteration on vpiEnumNet, vpiIntegerNet, and vpiStructNet VPI objects has been disabled as it was incomplete and unsafe to use. * Code coverage does not appear for some very simple VHDL processes that act as a simple clocked-D flip-flop. This process is optimized away in such a way that it is currently unavailable to code coverage. This will be fixed in a future release. An example is: dff_async: PROCESS (clk,rst) BEGIN IF rst = '1' THEN im1 <= '1'; ELSIF clk'event AND clk = '1' THEN im1 <= im0; END IF; END PROCESS; ______________________________________________________________________ Product Changes to 6.5e * The breakpoint behavior of the -cond option has changed to re-parse expressions each time the breakpoint is hit. This allows expressions with local references to work. Note that because of this change, condition expressions referencing items outside the context of the breakpoint must use absolute names. This is different from the previous behavior where a relative signal name would be resolved at the time the bp command was issued, allowing the breakpoint to work even though the relative signal name was inappropriate when the breakpoint is hit. * Errors involving assignments to enums in vlog, vopt, or vsim are now printed using message #8386, which is suppressible. * In previous versions of the simulator, a random seed was sometimes assigned to processes created for non-blocking-assignments, and this could affect random-stability, depending on optimizations that were in effect. In 6.5, this is no longer the case; but it may result in different results involving randomization from 6.4x. * FSM recognition reporting in the coverage FSM flow has been made consistent with the FSMDEBUG flow. Both flows will only dump the number of FSMs detected by default. The -fsmverbose option can be used to display FSM RECOGNITION INFO, if required. * The default keyboard shortcuts for the cut/copy/paste operations have been changed to match the Windows standard of Control-X/C/V respectively. A new preference setting (Main/PCEditBindingsOnUnix) category has been added to control this. Note, any opened text windows at the time the preference is changed will not see the change until the next time the GUI is started. * A new search capability has been added for all windows that previously supported use of the Contains toolbar and/or the "Edit > Find..." menu. This new "Search Bar" will appear along the bottom edge of the window it's being used from. It completely replaces the old Contains toolbar and individual Find dialog boxes. For those windows that support both filtering and finding, the mode for the Search Bar would need to be set accordingly (the last selected mode for the Search Bar is remembered between sessions). The various ways of choosing the mode are: + use Control+M while the Search Bar has the keyboard focus + select the mode from the Search Bar's menu (located on icon at far left) + click the label text which indicates the current mode The current mode of the Search Bar is displayed as a text label to the left of the type-in field, as well as by the icon located at the left edge of the type-in area. The main benefit of having the filtering functionality within the Search Bars is that each window now has its own unique type-in field as opposed to having to share the common Contains toolbar. The latter could lead to confusion over what is shown in the toolbar and the filtered content of the windows. There is also a simple history mechanism to allow saving search strings for later use. The keyboard shortcuts to support this are: + Control+S -- save current search text into history list + Control+P -- retrieve previous search text + Control+N -- retrieve next search text * You must now change the encoding of your character representations with the encoding system command, where the syntax is: encoding system To obtain a complete list of options, use the encoding names command with no arguments. Previously you could perform this action with the View > Encoding menu, which has been removed. * The VPI compatibility for this release defaults to the 2009 IEEE 1800 standard. This introduces, among other things, new VPI types for packed arrays of struct nets and struct variables. Normative files vpi_user.h, sv_vpi_user.h and vpi_compatibility.h are supplied with the latest known standardized contents. Users should however be aware that at the time of release the IEEE 1800-2009 was not complete. * Event order differences between an optimized and unoptimized design have been reduced with this release. Specifically, event propagation through Verilog zero-delay continuous assignment and primitive networks has been changed such that optimizations involving these networks are much less likely to result in behavioral differences. However, note that a design depending on the old event ordering may not behave the same with this release. Both, the unoptimized and optimized behavior may change, but should match each other more closely. Ideally, "races" should be removed from the design, but, if desired, the user may revert back to the old event ordering by specifying the -noimmedca vsim option or by setting the following line in the modelsim.ini file: ImmediateContinuousAssign = 0 * Code coverage information is no longer saved under design units in UCDB files. Instead, code coverage data for design units are constructed on-the-fly when a UCDB file is opened in IN_MEMORY mode. The information is constructed by merging all code coverage data from instances in the UCDB into the corresponding design unit. This has two main implications for UCDB API users: 1. Using APIs to create code coverage data under design units is not allowed anymore and the API calls will error out. 2. Opening UCDB files in read-streaming mode will not generate callbacks under design units since there is no code coverage data anymore. * The PrefMain(ShowFilePane) preference is now obsolete. The Files pane will follow current layout as do all other windows. * The view * command is now obsolete. The argument "*" will be ignored with no note warning or error. A window name or window name prefix must be supplied in order to open or configure any windows. * When a non-existent entry of an associative array is read, a default value is returned. We now re-initialize that value each time, in case the user modified it. The exception is if the user set an explicit default value. For example: integer bar[integer][$]; // Assoc. array of queues. task execute(); // Below, bar[2] doesn't exist, so we return the default value, // an empty queue. The user is pushing 777 onto it. bar[2].push_back(777); // Referencing bar[2] again now returns an empty queue. In previous // versions, we returned {777}. The $display now prints 'x'. $display ("bar [2][0] = %0d", bar[2][0]); * Some changes have been made to toggle coverage specific vsim command-line options. + The -togglevlogints option has been removed as SystemVerilog integer types are now supported for toggle coverage by default. + The following vsim command-line options have been changed as they were inconsistent with our convention. o -togglenoints CHANGED TO -notoggleints o -togglenovlogints CHANGED TO -notogglevlogints * We now treat a slice of a string as a string. This seems obvious, but it is not described anywhere in the LRM. The following is now supported: string line = "Hello there"; string targ; initial targ = line[0:5]; * The option -fsmdebug has been deprecated. A new letter code 'f' has been added to +acc to enable FSM detection and debugging. This also makes it possible to have module and instance bases selection with FSM debug. +acc without any letter code with automatically enable +acc=f. * Conditional timing check expressions are displayed as they appear in the HDL description. In the past equivalent conditions were displayed. For example: &&& (cond === 0) was displayed as &&& (~cond) * In some cases the -vmake flag will be required to correctly capture Verilog source file dependencies. * Invalid vsim command line switches used with -load_elab will now by default generate a warning message and not an error message. The warning message has a Message Id associated with it and is thus suppressible. ______________________________________________________________________ New Features Added to 6.5e * GNU make for Cygwin version 3.81 no longer supports dependencies with Windows style paths of the form C:/ in makefiles. The -cygdrive option to vmake generates a makefile that uses the /cygdrive/c style of path when generating dependencies. A Windows style path is still allowed as an argument to the compiler or simulator. * A new preference variable, PrefSource(NoDBS), is added to toggle loading the Symbol Database files during simulation. * Added support for generics of type boolean at the SV-VHDL language boundary for cases when VHDL instantiates a Verilog module. * sccom is enhanced with two new options that enable the creation and use of multiple systemc.so(s). * -linkshared Create an intemediate SystemC shared library. This option cannot be used with -link * -libshared Specify the library that contains the intermediate SystemC shared library. These options are not supported on the Windows platform