文档资料 许可 在线购买 下载 全部页面 技术资料 产品型号

主页   |   产品   |   支持   |   最终市场   |   技术中心   |   教育与活动   |   公司介绍   |   在线购买

培训中心   |   大学计划   |   网络研讨会   |   演示   |   活动日程

在线演示    设计软件           Quartus II简介           基础 FPGA/CPLD 设计           设计流程           设计优化           减少设计周期           验证       嵌入式处理器

主页 > 教育与活动 > 演示 > 设计软件 > 设计优化 打印此页 发送此页 Quartus II Software Online Demonstrations—Design Optimization and Implementation The Quartus® II software optimizes design performance to reach timing closure faster. The demonstrations listed in Table 1 provide an overview of available Quartus II features that help optimize design performance. Table 1. Design Optimization and Implementation Resources Topic Self-Running Demonstrations (Playing Time) Documentation Training Courses Solutions/ Technical Support Integrated Cross Probing (5 minutes 32 seconds) Design Implementation and Optimization (PDF) volume of the Quartus II Development Software Handbook Analyzing Synthesis Results With the Quartus II RTL and Technology Map Viewers (PDF) section of the Quartus II Development Software Handbook The Quartus II Software Design Series: Foundation (Instructor-led, one day) The Quartus II Software Design Series: Verification (Instructor-led, one day) Optimization Advisors Provide Design-Specific Suggestions to Improve Design Results (4 minutes 16 seconds) Optimizing Designs for Altera® Devices (PDF) section of the Quartus II Development Software Handbook The Quartus II Software Design Series: Optimization (Instructor-led, one day) Using the RTL Viewer and Technology Map Viewer to Check Synthesis and Fitting Results (5 minutes 12 seconds) Analyzing Synthesis Results With the Quartus II RTL and Technology Map Viewers (PDF) section of the Quartus II Development Software Handbook The Quartus II Software Design Series: Foundation (Instructor-led, one day) The Quartus II Software Design Series: Verification (Instructor-led, one day) The Quartus II Software Design Series: Optimization (Instructor-led, one day) Using I/O Assignment Analysis to Validate Pin Assignments Early (4 minutes) I/O Management (PDF) chapter of the Quartus II Development Software Handbook Design Planning Guidelines for High-Density FPGAs (Online, one hour) I/O Management  (Online, one hour) The Quartus II Software Design Series: Foundation (Instructor-led, one day) The Quartus II Software Design Series: Verification (Instructor-led, one day) Timing Closure Floorplan (5 minutes 21 seconds) Design Optimization for Altera Devices (PDF) and Timing Closure Floorplan (PDF) chapters of the Quartus II Development Software Handbook Design Planning Guidelines for High-Density FPGAs (Online, one hour) The Quartus II Software Design Series: Foundation (Instructor-led, one day) The Quartus II Software Design Series: Optimization (Instructor-led, one day) Netlist Optimization Improves Push-Button Results (4 minutes 51 seconds) Design Optimization for Altera Devices (PDF) and Netlist Optimization (PDF)  chapters of the Quartus II Development Software Handbook The Quartus II Software Design Series: Optimization (Instructor-led, one day) Using Design Space Explorer to Increase Design Performance (2 minutes 49 seconds) Design Optimization for Altera Devices (PDF), Timing Closure Floorplan (PDF), and Design Space Explorer (PDF) chapters of the Quartus II Development Software Handbook The Quartus II Software Design Series: Optimization (Instructor-led, one day) 给本页评分

请填写反馈意见   注册索取最新邮件通知

主页 | 产品 | 支持 | 最终市场 | 技术中心 | 教育与活动 | 公司介绍 | 在线购买  培训中心 | 大学计划 | 网络研讨会 | 演示 | 活动日程  联系我们 | 站点帮助 | 网站导航 | 个人信息 | 法律申明  Copyright © 1995-2008 Altera International Limited, 香港九龙观塘观塘道388号创纪之城1期1座9楼11-18室 Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus和MegaCore是Altera公司的商标。