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Available Now On-Demand! |
Overview
As designs become more complex and FPGA densities increase, it’s important to know how your tools can reduce compile times for faster timing closure. Incremental compilation, a feature that enables advanced flows to achieve fMAX gains, targets specific design areas while preserving performance in the areas of the design that haven’t been changed.
An introduction to incremental compilation, this net seminar describes how to use this feature to shorten overall design time.
You’ll learn how to:
- Use a top-down incremental design approach to cut compile times
- Automatically generate scripts for a partitioned design to eliminate overlapping constraints using a bottom-up flow
- Shorten debugging cycles by recompiling only the debug logic portion
- Reduce compile times while preserving performance
Who Should View
- Engineering Management
- FPGA Designers
- ASIC Designers
Drawing
All participants who attend this net seminar between January 9, 2007 and January 23, 2007 and complete the post-presentation survey will be entered into the drawing for a chance to win an Epson P-2000 Multimedia Storage Viewer (US$500)!
Presenters
Darren Aalami
Sr. Technical Marketing Engineer, Software and Nios Marketing
Darren Aalami has been with Altera since 2003, where he’s in Software and Nios® Marketing with responsibility for the technical marketing of Altera’s Quartus II software. Prior to this role, Darren worked at Xilinx for eight years in applications, project management, field sales, and partner relations. Darren holds a BSEE from the University of California at Irvine and is currently pursuing an MBA from Santa Clara University.
Terry Borer
Supervising Senior Member of Technical Staff
Terry Borer has been with Altera since 2000. He manages a software group responsible for various projects including incremental compilation, LogicLockTM and the Design Space Explorer. Terry holds BASc and MEng degrees from the University of Toronto.
