Learn Best Board Design Practices for Power Delivery Network Net Seminar
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Available Now On-Demand!
Featured Technology: Stratix II® GX, Stratix II, Cyclone® II, Stratix
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Overview
The power delivery network (PDN) is a critical design component in board designs, especially for high-speed systems. A robust PDN is required to achieve a high level of system signal integrity. In this net seminar, the SI Doctor, Dr. Eric Bogatin, provides detailed practical strategies for achieving low PDN impedance. Dr. Bogatin covers voltage regulator modeling and simulations and techniques to estimate and achieve PDN target impedance. He also provides a close look at profiles and the proper selection of decoupling capacitors.
You’ll learn how to:
- Establish PDN target impedance
- Select the right voltage regulator module (VRM)
- Design a proper board-level decoupling network to meet your system requirements
Who Should View
- System Architects
- Hardware and system design engineers
- FPGA developers
- Engineering & technical managers
Presenters
 
Dr. Eric Bogatin
President, Bogatin Enterprises, LLC
Eric received his BS in physics from MIT and MS and PhD in physics from the University of Arizona in Tucson. He has held senior engineering and management positions at Bell Labs, Raychem, Sun Microsystems and Ansoft. He is currently the President of Bogatin Enterprises, a leading provider of signal integrity training. Eric has written 4 books on signal integrity and interconnect design and over 200 papers. His latest book, Signal Integrity- Simplified, was published in 2004 by Prentice Hall. He has taught over 4,000 engineers in the last 20 years. Read his monthly signal integrity column, "No Myths Allowed," in Printed Circuit Design & Manufacture magazine. Many of his publications are available for download from his web site, www.BeTheSignal.com
Subianto Windoro
Sr. Manager, Technical Analysis High-End FPGAs
Subianto Windoro has been with Altera since 1997, where he now manages the Technical Marketing Group for High-Density FPGA products. He leads the effort in technical product analysis of parallel and serial I/O interconnects, signal integrity and FPGA architecture and technology solutions. His experience covers all aspects of programmable solutions, including device, software and tools. Windoro holds a master’s degree in electrical engineering from Purdue University.
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