Signal & Power Integrity Design Techniques for SSN
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Available Now, On-Demand
October 2, 2007–October 1, 2008
Featured Technology: Stratix® III FPGAs
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Overview
With today’s stringent requirements for high-speed memory and serial interfaces, designers are looking for the best techniques for dealing with simultaneous switching noise (SSN). Meeting performance goals for near- and far-end SSN, as well as power supply quality, are key to a design’s success.
This webcast teaches signal integrity design techniques to mitigate SSN, including how to maintain power integrity. You’ll learn about measurement criteria, measured results, and data on design prototypes and simulation predictions.
At the net seminar, you’ll learn how to:
- Identify SSN mechanisms
- Quantify SSN as a percentage of signal swing
- Improve SSN on your system
Who Should View
- System architects
- Hardware and system design engineers
- FPGA developers
- Signal integrity engineers
Presenters
Larry D. Smith
Principal Engineer, Altera
Larry D. Smith is a principal engineer at Altera with expertise in SSN noise, power, and signal integrity. Prior to joining Altera in 2005, he worked at Sun Microsystems from 1996 to 2005 where he did development work in the field of signal and power integrity. Before this, he worked at IBM in the areas of reliability, characterization, failure analysis, power supply and analog circuit design, packaging, and signal integrity. Mr. Smith received a BSEE degree from the Rose-Hulman Institute of Technology and a MS degree in material science from the University of Vermont. He has 13 patents and has authored numerous journal and conference papers.
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