Available Now, On-Demand
Length: 23 minutes
Did you know that it's possible to have both the performance of hand-optimized HDL and the productivity benefits of design reuse? See how Altera's DSP Builder Advanced Blockset lets you optimize your large design's performance while reducing design iterations.
Using a sensor (radar) front-end design example on a large FPGA, you'll see how DSP Builder simplifies and speeds your design process.
View the 23-minute webcast and demo to learn how to :
- Generate highly optimized HDL using a high-level Simulink tool flow
- Specify and design to your clock rate requirements
- Easily close timing on large designs at 350+ MHz clock rates
- Support multi-channel, poly-phase, high-performance DSP datapaths
- Efficiently implement FIR and FFT functions
Presenter:
Michael Parker
Senior DSP Technical Marketing Manager
