Digital television (DTV) modulators perform video transport framing, forward error encoding, filtering, and mapping binary data into various modulation constellations. The International Telecommunications Union (ITU) standardized the J.83-A/B/C specification for cable modulation schemes used for transmission of digital video and audio for different geographies. ITU-T J.83 Annex B describes the framing structure, channel coding, and modulation schemes for digital cable service in North America. J.83 Annex A and J.83 Annex C defines the cable modulation schemes for Japanese and European regions, respectively.
Figure 1 shows a block diagram of a generic cable QAM for Annex B.
Figure 1. Generic J.83B Cable Modulation Block Diagram
Transport Stream Interface and Framing
The J.83-based modulator receives video data either in asynchronous serial interface (ASI) or MPEG-2 serial peripheral interface (SPI) transport stream (TS) format. Once the TS data is received, it goes through the J.83 recommendation for video framing.
Coding and Interleaving
The J.83B standard employs a forward error correction (FEC) coding that implements the encoding in stages. The main steps are Reed-Solomon (RS) encoding and variable length interleaver followed by trellis coded mapping for modulation. The RS encoder takes the MPEG-2 TS packets, calculates the parity bytes, and adds them to the MPEG-2 TS packets so that the receiver can validate the integrity of the received packets. The interleaver spreads out the sequential order of the data to prevent adjacent burst errors.
In FEC encoding, the data multiplexing and barrel shifters represent the bulk of the logic resources required. The innovative logic structure in Altera® Stratix® II devices is well suited to efficiently implement high-performance barrel shifters by allowing the construct of up to two, six-input functions in a single adaptive logic module (ALM). Also, the interleaver in the FEC encoder requires heavy use of memory that can be easily addressed by the TriMatrix memory in Stratix II devices.
For more information on how Stratix II devices benefit the QAM modulator design, refer to the Versatile Digital QAM Modulator (PDF) white paper.
Mapping and Modulation
Trellis Coded Modulation (TCM) is an encoder that selects an optimal sequence from the data stream and a map of the QAM constellation. The constellation in TCM is usually larger than required for the data stream, and the encoder generates a sequence of wider words mapped such that the transition distances in the constellation are maximized. This increases the distance of transitions over that data-stream sequence, thus improving the signal-to-noise ratio. The modulation is QAM with a 64QAM or 256QAM constellation.
The mapped data pairs are upconverted to an intermediate frequency before transmitting.The digital upconverter (DUC) translates signals from a baseband frequency to the intermediate frequency. The numerically controlled oscillator (NCO) is the key component for the DUC.
Altera Solutions
Altera’s intellectual property (IP) partner Commsonic offers a J.83-A/B/C QAM modulator MegaCore® function, which is fully compliant with the European, U.S., and Japanese cable standards. The core provides all the necessary functions between TS input and QAM baseband output. The core targets Cyclone® II and Stratix II device families and can be configured to support from one to four frequency division multiplexing (FDM) channels with additional (independent) channels accommodated by the instantiation of multiple single or multi-channel cores per FPGA.
Table 1 lists Comsonic J.83 offerings and their device utilization.
| Table 1. Typical Device Utilization for Altera Megafunctions | ||||
| Device | Configuration | Logic Elements (LEs) | 9 x 9 Multipliers | M4K RAM |
|---|---|---|---|---|
| EP2C20 | 1-channel DVB-C | 11k, 31% | 52, 100% | 36, 69% |
| EP2C35 | 4-channel J.83B (short interleave) | 27k, 82% | 70, 100% | 100, 95% |
| EP2C35 | 4-channel J.83B (long interleave) external RAM | 27k, 82% | 70, 100% | 36, 34% |
| EP2C70 | 1-channel J.83B (long interleave) | 9k, 13% | 84, 28% | 161, 37% |
| EP2C70 | 8-channel J.83B (short interleave) | 43k, 64% | 288, 96% | 192, 76% |
Altera’s low-cost Cyclone III FPGAs are built on a 65-nm, low-power process technology. The Cyclone III family is composed of eight devices ranging from 5K to 120K logic elements (LEs) and up to 534 user I/O pins. Cyclone III FPGAs offer up to 4 Mbits of embedded memory, 288 embedded 18 x 18 multipliers, and dedicated external memory interface circuitry, making them ideal for implementing applications such as a QAM modulator in digital broadcasting applications.
