cdma2000 Network
The cdma2000 third-generation (3G) wireless system is based on the code-division multiple access (CDMA) system. The cdma2000 system delivers high-bandwidth data and voice services to users of mobile equipment. Figure 1 shows the infrastructure of a cdma2000 wireless network. Altera® devices can be used in each of the nodes shown in the figure.
Figure 1. cdma2000 Wireless Network Infrastructure
cdma2000 Infrastructure Nodes:
- BTS: Base transceiver station
- BSC: Basestation controller
- MSC: Mobile switching center
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- PDSN: Packet data serving node
- HA: Home agent
- IWF: Interworking function
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The 3GPP2 website contains more information on the cdma2000 specifications.
cdma2000 Infrastructure Node Architecture
The cdma2000 infrastructure node can be built on an Internet protocol router. It consists of a host processor, adjacent node interfaces, and switch fabric. Figure 2 shows the architecture of a cdma2000 infrastructure node.
Figure 2. cdma2000 Infrastructure Node Architecture
In the Figure 2, the adjacent node interface and the switch can be implemented in programmable logic. Together, they form the voice and data path. An Internet protocol router is used to transport packet voice and data within the cdma2000 wireless network. Figure 3 shows a packet voice and data path implementation.
Figure 3. Packet Voice & Data Path Functional Blocks
Select from the colored blocks in the diagram for more information.
The main functions of the packet voice and data path implementation shown above are:
- Physical Layer Processing—The physical layer processing function processes SONET/SDH or T/E/J frame headers and extracts point-to-point protocol (PPP) packets on the receiver side. On the transmitter side, it places PPP packets into the frame payload and adds the frame header.
- Higher Layer Processing—The higher layer processing function performs parsing, framing, packet classification, and modification. Encryption and compression processors are usually supported and special processors are often used to accelerate the process. The queuing and traffic manager function places packets on different priority queues and drops packets according to the traffic condition.
- Switching—The switch fabric performs switching and routing functions for voice and data. It also contains a queue manager.
- Control and Management—The control and management function performs path control and collects data for management purposes.
Altera & AMPPSM IP Cores
The following intellectual property (IP) cores are available on the IP MegaStore™ website:
The Altera Advantage
Using Altera products for your 3G wireless network offers the advantages listed below:
Time-to-Market
The 3G wireless network market is very competitive, making time-to-market particularly important. Using Altera FPGAs and intellectual property cores saves vital time, since designers no longer have to wait for the turnaround times necessary for ASIC development.
Flexibility
The migration to 3G will require multiple revisions, and will not occur in one step. As a result, ASICs are not a viable platform. Altera's FPGA solutions provide the flexibility to implement new proprietary features and perform remote in-field upgrades.
Embedded DSP Blocks
Stratix® II DSP blocks consist of hardware multipliers, adders, subtractors, accumulators, and pipeline registers. The DSP blocks are flexible, efficient, and optimized for a variety of DSP applications requiring high data throughput, making the blocks ideal for wireless communications.
High-Bandwidth Differential I/O Support
Altera Stratix II devices with differential I/Os (LVDS and HyperTransport™) support allow designers to meet high-bandwidth needs with up to 152 receiver and 156 transmitter channels operating at up to 1 Gbps per channel.
Nios II Embedded Processor Solutions
The Nios® II embedded processor is based on the highly successful and revolutionary concept of embedding soft embedded core RISC processors within FPGAs. The advanced architectural features of Stratix II FPGAs, combined with the Nios II embedded processor, offer unparalleled processing power to meet the needs of high-bandwidth systems.
Quartus II Software
When combined with Altera intellectual property cores and the library of parameterized modules (LPM), Quartus® II development software makes the design process even faster and easier. Functions can be plugged into a design directly, and most can be accessed through the MegaWizard® Plug-In user interface and customized with just a few clicks.
Cost-Reduction Path
System designers implementing wireless applications using Altera high-density FPGAs may need a low-risk cost-reduction path for high-volume production. Those designers can migrate their designs from an FPGA to a HardCopy® II structured ASIC. For example, time-sensitive wireless applications can be prototyped and ramped up into production using Altera FPGAs, and when the design is ready for high-volume production, the design can be migrated to HardCopy II structured ASICs, thus reducing overall costs.
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