Access
The Access market requires low-cost solutions. Altera is uniquely positioned to address this by offering FPGAs geared for low-cost applications and also a path to reducing cost with structured ASICs. In addition, Altera provides robust solutions to enable quick time-to-market and low-cost implementations of:
Overview
Altera and our partners can support your development methodology, whether you want to develop your multi-service access node (MSAN) application in-house or buy an off-the-shelf solution. A programmable platform allows you to scale your design across applications, features, and data rates. You will be able to swiftly incorporate new features, operator requirements, and density variations.
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In-House Development—You develop specialized intellectual property (IP) using building blocks available from Altera or third-party IP partners. Altera can help mix and match flexible, modular functional blocks to your exact requirements. You assemble the final solution and maintain ownership and control, all with less design effort and time.
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Off-the-Shelf Solution—You define the application specifications and turn to our partners for complete turnkey solutions, achieving faster time-to-market and lowering your overhead costs.
Typical Access Cards
Figure 1 shows a generic MSAN block diagram.
Figure 1. Generic MSAN Block Diagram
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Altera Solutions in Access
Table 1 shows Altera's Access solutions.
| Table 1. Altera Access Solutions |
| GPON Application |
Develop In-House |
Buy Off-the-Shelf |
|
OLT MAC
|
Stratix® II GX FPGAs, HardCopy® II structured ASICs
|
- |
|
Ethernet MAC
|
10/100/1000 MAC and 10-Gbit MAC cores from MoreThanIP
|
- |
|
Traffic Aggregation and Management
|
10-Gbps traffic management reference design, 10-Gbps RLDRAM II packet memory controller reference design, two-level scheduler reference design, and hardware validation platform
|
5-Gbps NPU IP core, 10-Gbps classification IP core, 10-Gbps search IP core, five-level hierarchical scheduler, and 10G DDR2 packet memory controller
|
|
Up to 20-Gbps Packet Processing
|
Packet processing modules and framework from Altera, including:
Stratix series FPGAs, Cyclone® series FPGAs, and Nios® II embedded processors
|
Ethernity ENET3000 access flow processor and carrier Ethernet and multi-protocol label switching (MPLS) NPU
|
|
DSL Channel Bonding
|
- |
Custom-built solution from AimCom
|
|
Reed-Solomon for Forward Error Correction (FEC)
|
Aliathon FEC core, Altera Reed-Solomon Compiler
|
- |
Performance and Scalability Options
- Altera® Nios II soft processors can be used for a variety of Access functions, including packet processing. These solutions can be scaled by instantiating additional Nios II cores inside the FPGA architecture.
- Altera Stratix GX and Stratix II GX transceivers are ideal for 1- to 3.125-Gbps backplane interface applications and conform to XAUI jitter tolerance, transfer, and generation parameters.
- Triple-speed Ethernet MAC cores allow the support of 10, 100, and 1000 Mbps Ethernet MACs in a single solution.
Altera Design Advantage in Access
- Low-Cost Leader—Access platforms require low-cost components. Altera has developed Cyclone III FPGAs and MAX® II CPLDs to address the requirements for low-cost programmable solutions. Also, Altera’s HardCopy structured ASIC architecture provides a cost migration path for high-performance and high-volume production deployments.
- Access Packet Processing and Traffic Management—The combination of Altera’s Cyclone III FPGAs and Altera’s Nios II soft core processors can address many packet processing requirements for the Access market.
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