Switch fabrics comprise the central interconnect architecture for all enterprise, access, and edge networking systems. The fabric interface chip (FIC), which fits between the network processing unit (NPU) and switch fabric devices, must stream traffic efficiently from 2.5 Gbps to 10+ Gbps with good signal integrity. At the same time, it must also support key fabric requirements such as data throughput, flow control, and pre-flow queuing.
High-performance FPGAs with embedded transceivers can support the bandwidth and density requirements for both the FIC and switch fabric in many wireline systems. For example, our Stratix® V FPGAs, with up to 66 transceivers operating from 600 Mbps to 12.5 Gbps, can support up to 825 Gbps of bandwidth for switch fabric applications. Also, the device's transceivers provide backplane drive capabilities and the devices support a variety of serial communication protocols.
Figure 1 shows a block diagram of a central switch fabric with embedded scheduling and buffering.
Figure 1. Switch Fabric Block Diagram
