Protocol Bridges
FPGAs provide an efficient, re-configurable platform for implementing many different types of multi-port peripheral device bus protocol aggregation and switching solutions. Altera designed the Stratix® II, Stratix II GX, and Stratix GX devices to support many different electrical interfaces in a wide variety of full-duplex device bus protocols. These devices also embed single- and dual-port memory structures that can be configured for various packet and cell buffering architectures. These features provide the foundation for dynamically reconfigurable, full-duplex protocol conversion solutions, which enable more efficient silicon utilization, improve system configuration, and reduce component cost, system power, and time to market.
Protocol conversion solutions consist of packet aggregation and switching devices that interconnect high-speed network processing units (NPUs) and traffic management devices to multiple low-speed peripheral device bus protocols, which can interface to packet interface devices (e.g., media access control (MAC)/PHY/framer), encryption devices, digital signal processors, time-division multiplexed (TDM) I/O devices, and others. Maintaining efficient data flow between the low-speed interfaces (SPI-3) and the high-speed interface (SPI-4.2) requires the ability to control various parameters such as port number mapping, buffer memory size, and FIFO queue watermarks for handling flow control. Figure 1 shows a block diagram for a Quad SPI-3-to-SPI-4.2 packet aggregation device.
Figure 1. Quad SPI-3-to-SPI-4 Packet Aggregation
Quad SPI-3-to-SPI-4 Packet Aggregation Solution Overview
The Quad SPI-3-to-SPI-4.2 packet aggregation device provides bidirectional physical and logical translation, and it multiplexes/de-multiplexes four SPI-3 interfaces to one SPI-4 interface. You can map each of the SPI-3 interface channels to one of 16 channels on the SPI-4.2 interface. The aggregation device performs protocol encapsulation, independent clocking on each interface, and automatic rate adaptation, as well as supporting 12.8-Gbps data throughput in each direction. Each interface supports configurable sink/source channel FIFO sizes, automatic sink flow control, per-channel source flow control processing and credit management, and automatic handling of Maxburst1 and Maxburst2 per channel.
One of the most common uses of the Quad SPI-3-to-SPI-4.2 packet aggregation device is to bridge between different buses at different bandwidths. This is a critical function to any communications system that tries to aggregate multiple framers into a traffic manager or a network processor.
Figure 2 shows the block diagram for the Interlaken-to-SPI-4.2 bridge. In this example, the bridge connects two SPI-4.2 interfaces, each transferring 10 Gbps of data to one Interlaken interface.
Figure 2. Interlaken-to-SPI-4 Bridge (20-Gbps Full Duplex Line Example)
Note:
- NPU = network processing unit.
Interlaken-to-SPI-4 Bridge Solution Overview
Interlaken is a scalable chip-to-chip interconnect protocol designed to enable transmission speeds from 10 Gbps to 100 Gbps and beyond. Using the latest serializer/deserializer (SERDES) technology and a flexible protocol layer, Interlaken minimizes the pin and power overhead of chip-to-chip interconnect and provides a scalable solution that can be used throughout an entire system.
Using Altera's POS-PHY Level 4 MegaCore® functions and Sarance's Interlaken IP (IIPC) core, an Interlaken-to-SPI-4.2 bridge is easily constructed. Sarance’s IIPC family is a highly efficient implementation of Interlaken. The IIPC core is available today for FPGA implementation. The FPGA implementation is specifically optimized to take advantage of the advanced structures available in modern FPGAs. The family consists of cores ranging from 10 Gbps to 40 Gbps, supporting any number of SERDES lanes. Each core is fully compliant to the Interlaken revision 1.1 specifications and provides a cost effective, risk free, and quick time-to-market solution. In addition, Interlaken uses two levels of cyclical redundancy check (CRC) and a self-synchronizing data scrambler to ensure data integrity and link robustness.
SPAUI Solution Overview
SPAUI, an interface based on the XAUI industry standard, incorporates several extensions to support dense 10 Gbps-level applications with speedup to accommodate such factors as packet headers, full rate 12GE, and in-band flow control. Incorporating several developed extensions such as channelization, packet interleaving, and enhanced flow control, SPAUI combines the benefits of both XAUI and SPI-4.2 standards into a single interface supporting MAC/framer, network processing unit (NPU), and traffic management requirements.
SPAUI features include:
- Incremental changes from standard XAUI and 10GE standard
- Fully compatible with XAUI
- High speed, up to 24 Gbps
- Optional in-band flow control
- Optional out-of-band flow control
- Support for 256 channels
- Support for channel burst interleaving
- Altera implementation-friendly
- Easily bridgeable to SPI-4.2
The SPAUI memorandum is available for free upon request from Dune Networks.
Altera is partnered with MoreThanIP and Octera who have experience with SPI-4.2-to-XAUI variant bridges.
Altera and AMPP Cores
The following cores are available from Altera and Altera Megafunction Partners Program (AMPPSM) partners:
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