Universal Front End
Due to the increasing demands of supporting multiservice networks in a highly flexible architecture, communication system designers are challenged to design systems supporting an increasing list of protocols, encapsulation schemes, and data rates.
Example protocols include Sonet/SDH, Ethernet, Fibre Channel, Resilient Packet Ring (RPR), Asynchronous Transfer mode (ATM), and Frame Relay (FR). New encapsulation schemes include standards such as the emerging generic framing procedure (GFP) and virtual concatenation (VCAT), as well as High-Level Data Link Controller (HDLC) and point-to-point protocol (PPP). These technologies must also be able to scale support rates such as 155Mbps, 622 Mbps, 1Gbps, 2.5Gbps, and 10Gbps.
You can address the mounting challenges of communication system design by integrating several functions into a high-density programmable logic device (PLD). For instance, you can integrate functions such as the SONET/SDH framer, ATM cell delineator, and packet interface into a single Altera® FPGA . Using multiple programmable files, this same FPGA can be reconfigured to support multiple configurations, creating a “universal” front end.
One Altera FPGA can be designed to support the transport of either ATM cells or PPP packets over SONET/SDH at a variety of different data rates (155 Mbps, 622 Mbps, and 2.5 Gbps). Designing a line card to support either the transport of cells or packets over SONET/SDH as separate PLD configuration options provides a highly optimized solution. You only pay for the gates that you require and are not burdened with the complicated software programming requirements of a multi-function ASSP chipset.
Inventory costs can be further minimized while retaining flexibility by storing multiple device programming files in flash memory. The PLD can be programmed at line-card boot up with the appropriate configuration (ATM over SONET/SDH STS-12c/STM-4, Packet over SONET (POS)/SDH STS-12c/STM-4, ATM over SONET/SDH STS-3c/STM-1, or Packet over SONET/SDH STS-3c/STM-1). By loading the PLD with only the required gates, the PLD size is minimized for each operating mode.
Altera & AMPP Cores
The following cores are available from Altera and Altera Megafunction Partners Program (AMPPSM) partners:
Related Links
|
 |
|
文档资料
> 
