Networking
Altera provides solutions to reduce media I/O costs, improve traffic aggregation, and increase packet throughput performance within routers and switches. These solutions include:
Overview
The environment of high-performance IP networks and the growing customer demand for internet bandwidth has placed excessive load on today’s network providers. To meet these demands, a new generation of routers that deliver more functionality, increased packet processing capabilities, and new feature sets is driving the need towards fully programmable fast path architectures.
Figure 1. Networking Topology
The networking segment includes multiservice edge switches, edge aggregation routers, IP service routers, multiservice core switches, and IP core routers.
Typical Router Cards
The basic system architecture for an edge router is shown in Figure 1. Today’s router architectures use distributed CPU designs that enable data flow of packets to proceed unimpeded along a fast path, while management functions such as route table updates are handled separately across a slow path. With centralized management and control CPU, line-card processing has evolved for delivering faster, wire-speed, forwarding. As networking requirements continue to driven by higher wire-speeds (e.g., OC-48, OC-192, 10 GbE) and more complex multi-services (e.g., IPv4, IPv6 MPLS, ATM, multicast, VoIP), new hardware need to assist passing packets from dedicated packet interfaces (UTOPIA-L2, SPI-3, SPI-4.2) on fixed function L1/L2 ASICs to programmable NPUs with very low processor overhead.
Figure 2. Edge Aggregation Router System Diagram
Exchanging packets between media I/O cards and packet forwarding engines requires the flexibility to aggregate multiple lower-rate interfaces (UTOPIA, POS-PHY-L2/L3, SPI-3) into a higher-rate interface like SPI-4.2. The data that enters on the media I/O module interface (SPI-3) has to be mapped to different channels and queued for transmission over the high-speed interface (SPI-4) and visa versa. A SPI-4-to-SPI-3 packet bridge is a natural FPGA solution that can be used for rate adoption, traffic switching, or traffic aggregation between multi-gigabit framers/MACs devices and network processors.
Altera Solutions in Networking
Performance & Scalability Options
- Altera® Stratix® GX and Stratix II GX transceivers are ideal for 1- to 3.125-Gbps backplane interface applications and conform to XAUI jitter tolerance, transfer, and generation parameters. Many networking backplanes are based on XAUI-like protocols. Stratix GX transceivers include up to 24 SERDES for use in mesh, star and dual-star backplance topologies.
- Altera Stratix GX, Stratix II, and Stratix II GX dynamic phase alignment interfaces support up to 1000-Mbps LVDS data rates and comply with the Optical Internetworking Forum (OIF) specifications for high-speed system packet interface (SPI-4.2). These devices also comply with the Optical Internetworking Forum (OIF) specifications for high-speed physical layer interface (SFI4 – 10Gbps SERDES/Framer Interface).
Altera Design Advantage in Networking
- Because system designers no longer can afford the luxury of long development cycles or custom hardware intensive ASIC-based architecture, they have rapidly embraced the advantages Altera’s FPGAs and HardCopy® structured ASICs bring to maximizing the return on their investment across programmable networking architectures.
- Developing routers and switches that use a programmable 10 Gbps fast path benefits designers in the following ways:
- Reducing cost by adding features to media I/O module without hardware replacement.
- Enables faster time-to-market for new features and services because deploying configuration updates is faster than spinning ASICs
- Delivering any service at any speed on any port – contrasting features-specific I/O modules with varying performance depending on ASIC version and features supported.
- Altera Quartus® II software development tools provides the design and verification tools needed to speed chip development and reduce time-to-market.
- The Altera MegaCore® and AMPPSM IP cores reduce development time by providing a wide range of industry standard framers, memory interfaces, NPU interface and packet processing blocks to accelerate the design of networking solutions.
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