The value of bundling services is accelerating carrier investment in triple-play networks. Managing these (voice, video and data) services on a common Internet protocol (IP) network will lead to a dramatic reduction in operational expenses. In addition, this migration to IP networks will enable carriers to offer enhanced services to drive increased revenues. These emerging services are the key to carrier growth and sustainability in the future. Supporting these future services requires a solution that meets today’s stringent quality of service (QoS) requirements, yet is flexible enough to adapt to tomorrow’s changing requirements.
Traffic Manager Solution Overview
Altera has a working 10-Gbps traffic manager solution targeting Stratix® II FPGAs. The inherent programmability of the FPGA allows the traffic manager to be adapted to support changing carrier requirements or emerging services. This traffic manager solution meets guaranteed line-rate performance for Ethernet, Packet over SONET/SDH, multiprotocol label switching (MPLS) and ATM traffic. The design was built in a modular fashion, enabling system designers to customize partial or complete sub-blocks of the traffic manager solution.
Figure 1. Traffic Manager Block Diagram
Customizable Traffic Manager Blocks
The modular sub-blocks can be customized to address specific market needs. Each of the sub-blocks within the Ingress and Egress Traffic Manager shown in Figure 1 represent individual register transfer level (RTL) modules. These sub-blocks can be customized or replaced for a given application.
10-Gbps Scheduler & Shaper
The scheduler is hierarchical, with configurable scheduling and shaping parameters. The scheduler can be extended to support up to 256K queues with 8 classes of service.
Figure 2. Hierarchical Scheduler
Queue Manager
The Queue Manager communicates with the scheduler and the memory controllers to manage the different queues. This function meets the performance requirements to handle 10-Gbps line rate traffic.
Multicast
Multicast replication is supported is supported on ingress and egress. The multicast block supports up to 4K multicast groups and 32K multicast leaves.
Congestion Control
Weighted random early detection (WRED) is supported, with queue depth configurable on all queues.
Data Path Interfaces
The example shown in the diagram utilizes Altera’s SPI-4.2 MegaCore® function for the data path interfaces. This can be modified to support SPI-3, Ethernet, or proprietary interfaces.
Memory Interfaces
Both the packet buffering and control memories utilize external RLDRAM II memories. This solution can meet the challenging latency and throughput requirements for 10-Gbps processing.
Demonstration Board
Altera has built a Traffic Manager Demonstration Board to showcase the functionality of the solution. The demonstration board contains two Stratix II FPGAs, one serving as the traffic manager and the other as the traffic generator. The demonstration can exist in a standalone environment, or the traffic generator can be bypassed with external test equipment generating traffic. To find out more information about Altera’s traffic manager solution, contact your local Altera sales representative.
Figure 3. 10-Gbps Traffic Manager Demonstration Board
Features & Benefits
- High-Performance
- Guaranteed 10-Gbps full-duplex line-rate performance in Stratix II
- High-speed RLDRAM II memory for packet buffering and pointer management
- Future-Proof
- FPGA configurability allows support for future services or changing requirements
- Multiple protocol support, including Ethernet, Packet-over-SONET, MPLS and ATM
- Support of emerging standards, such as Metro Ethernet
- Customizable
- Modular design enables sub-blocks to be customized
- Support for proprietary scheduling or queuing algorithms
- Scalable to support 2.5-Gbps and 10-Gbps applications
- Component Integration
- FPGA scalability enables integration of external components, such as packet co-processor
- Configurable data path interfaces eliminates external bridge
- Proven Solution
- Demonstrable in hardware
