Transmission
Altera provides solutions to address the convergence of Ethernet, SONET/SDH, Asynchronous Transfer Mode (ATM), Internet Protocol (IP), and Ethernet over SONET/SDH (EoS) technologies. These solutions include:
Overview
SONET/SDH is the dominant technology providing metro and long-haul transport in communications networks. SONET/SDH was originally optimized for carrying voice traffic, but increasingly carries data traffic. The growth of data transport has led to the emergence of standards for carrying Ethernet, fibre channel, and resilient packet ring (RPR) traffic over SONET/SDH.
Figure 1 shows the transmission segment, which includes SONET/SDH add-drop multiplexers (ADMs), digital cross-connects, coarse and dense wavelength division multiplexers (CWDM and DWDM), multiservice provisioning platforms (MSPPs), and optical switches.
Figure 1. Transmission Topology
Typical Transmission Cards
Line cards within the transmission segment can generally be classified into two categories: traditional SONET/SDH cards and emerging data processing cards.
Figure 2. Sonet/SDH Line Card
Notes:
- PHY = Physical Layer
- TSI = Time Slot Interchange
- FIC = Fabric Interface Card
- OTN = Optical Transport Network
The traditional SONET/SDH card enables traffic to be added and dropped from a SONET/SDH ring. SONET/SDH and optical transport network (OTN) traffic emerging on the line side can encapsulate voice, ATM, or packet traffic at rates ranging from 51 Mbps to 40 Gbps. The wide variety of line-side interfaces and encapsulated traffic has led to the development of modular cards that support multiple payload types and interface speeds. This enables carriers to reduce their card inventory and allows them to change the characteristics of the card upon deployment.
While SONET/SDH has the advantages of reliability and robust operations, administration, maintenance, and provisioning (OAM&P), it is inherently inefficient for intelligently transporting data traffic. This has led to standards targeting data transport in metro and core networks, including resilient packet ring (RPR)(IEEE 802.17), generic framing procedure (GFP)(ITU-T G.7041), virtual concatenation (VCat )(ITU-T G.707, 2000), and link capacity adjustment scheme (LCAS)(ITU-T G.7042).
Figure 3. Data Over Sonet/SDH Line Card
Notes:
- MAC = media access control
- PP = Packet Processor
- TM = Traffic Manager
- GFP = Generic Framing Procedure
- ESCON = Enterprise Systems Connection
- FICON = Fibre Connection
The data over SONET/SDH card leverages the existing 350K deployed SONET/SDH rings to transport data traffic. This card interfaces to RPR, Ethernet, fibre channel, and other storage and video protocols on the line side, and provides layer 2 and layer 3 processing in the packet processor and traffic manager. GFP is used to encapsulate the traffic more efficiently for the SONET/SDH-like backplane. Similar to the traditional SONET/SDH card, a modular card that flexibly supports the various line side protocols enables carriers to provision data services on demand.
Altera Solutions
Performance & Scalability Options
- The Altera® Stratix® GX and Stratix II GX transceiver FPGAs are ideal for 1- to 3.125-Gbps backplane interface applications and conform to XAUI jitter tolerance, transfer, and generation parameters. Many transmission backplanes are based on SONET/SDH-like protocols. The Stratix GX transceiver FPGAs include dedicated circuitry for SONET/SDH A1/A2 detection and can scale up to STS-48 (STM-16) in these applications.
- The Altera Stratix GX, Stratix II, and Stratix II GX dynamic phase alignment interfaces support up to 1000-Mbps LVDS data rates and comply with the Optical Internetworking Forum (OIF) specifications for high-speed system packet interface (SPI-4.2). These devices also comply with the OIF specifications for high-speed physical layer interface (SFI-4 – 10-Gbps SERDES/Framer Interface).
- The Framer and MAC cores scale from 10-Mbyte Ethernet or 51-Mbyte SONET/SDH up to 10-Gbyte Ethernet and 10-Gbyte SONET/SDH.
Altera Design Advantage in Transmission
- Proven Intellectual Property Solutions: Altera's MegaCore® and AMPPSM Intellectual Property cores reduce development time by providing a wide range of industry standard framers, memory interfaces, network processing unit (NPU) interfaces, and packet processing blocks to accelerate the design transmission platforms.
- Low-Cost Leader: Altera's low-cost Cyclone® III, MAX® II, and MAX 3000A devices provide cost-effective programmable solutions for transmission systems. Also, Altera's HardCopy® structured ASIC architecture provides a cost migration path for high-volume production deployments.
- Integration for Reduced Board Space and Power: As channel densities increase and form factors decrease, system integration becomes more critical. The integrated transceivers in Altera's Stratix GX and Stratix II GX families allow the flexibility to support varying protocols (Gigabit Ethernet, XAUI, PCI-Express, Serial RapidIO, 1G/2G Fibre Channel) and varying speeds on the same card. In addition, Altera's Nios® II soft processor can eliminate the need for external microcontrollers and microprocessors.
Related Links
|
 |
|
文档资料
> 
