|
Application Notes |
AN 532: An SOPC Builder PCI Express Design with GUI Interface 
Design Files for AN 532 (5 MB)
| 1.0 | Jun 2008 | 285 KB | AN-532-1.0 |
AN 531: Reducing Power with Hardware Accelerators
Design Files for AN 531 (1 MB)
| 1.0 | May 2008 | 151 KB | AN-531-1.0 |
| AN 530: Optimizing Impedence Discontinuity Caused by Surface Mount Pads for High-Speed Channel Designs
| 1.0 | May 2008 | 208 KB | AN-530-1.0 |
| AN 529: Via Optimization Techniques for High-Speed Channel Designs
| 1.0 | May 2008 | 690 KB | AN-529-1.0 |
| AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing
| 1.0 | May 2008 | 1 MB | AN-528-1.0 |
| AN527: Implementing an LCD Controller
| 1.0 | May 2008 | 344 KB | AN-527-1.0 |
| AN523: Cyclone III Configuration Interface Guidelines with EPCS Devices
| 1.0 | Jun 2008 | 963 KB | AN-523-1.0 |
AN 521: Cyclone III Active Parallel Remote System Upgrade Reference Design
AN521 Design Examples (1 MB)
| 1.0 | Jun 2008 | 1 MB | AN-521-1.0 |
| AN 520: DDR3 SDRAM Memory Interface Termination and Layout Guidelines
| 1.0 | Jun 2008 | 918 KB | AN-520-1.0 |
| AN 516: 10-Gbps Ethernet Reference Design
| 1.0 | Jun 2008 | 896 KB | AN-516-1.0 |
| AN 514: Power Optimization in Stratix IV FPGAs
| 1.0 | May 2008 | 221 KB | AN-514-1.0 |
| AN 479: Design Guidelines for Implementing LVDS Interfaces in Cyclone Series Devices
| 1.0 | Jun 2008 | 422 KB | AN-479-1.0 |
AN 469: Stratix III Design Guidelines 
| 1.1 | May 2008 | 628 KB | AN-469-1.1 |
| AN 466: Cyclone III Design Guidelines
| 1.1 | Jul 2008 | 1 MB | AN-466-1.1 |
AN 462: Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction
Example Design for AN 462: top.qar (2 MB)
| 1.2 | May 2008 | 888 KB | AN-462-1.2 |
AN 446: Debugging Nios II Systems with the SignalTap II Embedded Logic Analyzer
signal_tap_test software file (4 KB)
| 1.2 | Jun 2008 | 257 KB | AN-446-1.2 |
AN 445: Design Guidelines for Implementing DDR and DDR2 SDRAM Interfaces in Cyclone III Devices
AN 445 Design Example (1 MB)
| 2.1 | May 2008 | 2 MB | AN-445-2.1 |
AN 418: SRunner: An Embedded Solution for Serial Configuration Device Programming
Source Code (254 KB)
| 1.1 | Jun 2008 | 288 KB | AN-418-1.1 |
AN 408: DDR2 Memory Interface Termination, Drive Strength, Loading, and Design Layout Guidelines
Simulation Example (3 KB)
SIII_DDR2DIMM_RDWR.ffs (11 KB)
SIII_DDR2DIMM_RDWR.pjh (1 KB)
| 2.0 | Jul 2008 | 4 MB | AN-408-2.0 |
AN 386: Using the Parallel Flash Loader with the Quartus II Software
Flash Memory (873 bytes)
Nios Design (567 KB)
| 4.1 | May 2008 | 1 MB | AN-386-4.1 |
| AN 340: Altera Software Licensing
| 2.0 | May 2008 | 2 MB | AN-340-2.0 |
| AN 326: Interfacing QDRII+ & QDRII with Stratix II, Stratix II GX, Stratix, & Stratix GX Devices
| 5.1 | May 2008 | 2 MB | AN-326-5.1 |
| AN 311: ASIC-to-FPGA Design Methodology and Guidelines
| 3.0 | Jun 2008 | 386 KB | AN-311-3.0 |
| AN 518: SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices | 1.0 | May 2008 | 1 MB | AN-518-1.0 |
AN 517: Using High-Performance DDR, DDR2, DDR3 SDRAM with SOPC Builder
AN 517 Design Files (2 MB)
| 1.0 | Apr 2008 | 1 MB | AN-517-1.0 |
| AN 513: RapidIO Interoperability With TI 6482 DSP Reference Design | 1.1 | Jan 2008 | 2 MB | AN-513-1.1 |
| AN 512: Using the Design Security Feature in Stratix III Devices | 1.0 | Apr 2008 | 1 MB | AN-512-1.0 |
| AN 511: Polyphase Modulation Using a FPGA for High-Speed Applications | 1.0 | Feb 2008 | 279 KB | AN-511-1.0 |
AN 509: Multiplexing SDIO Devices Using MAX II CPLDs
AN 509 Design Example (721 KB)
| 1.0 | Dec 2007 | 198 KB | AN-509-1.0 |
| AN 508: Cyclone III Simultaneous Switching Noise (SSN) Design Guidelines | 1.0 | Dec 2007 | 379 KB | AN-508-1.0 |
AN 507: Implementing PLL Reconfiguration in Cyclone III Devices
Design Example 1: an507_de1_display.zip (204 KB)
Design Example 2: an507_de2_dynphase.zip (84 KB)
| 1.0 | Jan 2008 | 739 KB | AN-507-1.0 |
| AN 506: QR Matrix Decomposition | 2.0 | Mar 2008 | 371 KB | AN-506-2.0 |
AN 504: DSP System Design in Stratix III Devices
Design Example 1: Parallel FIR (79 KB)
Design Example 2: Multi-Channel FIR (20 KB)
Design Example 3: MAC_FIR (vhdl) (21 KB)
Design Example 4: Large Mult_Add (11 KB)
| 1.0 | Feb 2008 | 1 MB | AN-504-1.0 |
| AN 503: Implementing OFDM Modulation for Wireless Communications | 1.0 | Jan 2008 | 268 KB | AN-503-1.0 |
AN 502: Implementing an SMBus Controller in MAX II CPLDs
AN 502 Design Example (2 MB)
| 1.0 | Dec 2007 | 129 KB | AN-502-1.0 |
AN 501: Pulse Width Modulation Using MAX II CPLDs
AN 501 Design Example (279 KB)
| 1.0 | Dec 2007 | 104 KB | AN-501-1.0 |
AN 500: NAND Flash Memory Interface with MAX II CPLDs
AN 500 Design Example (187 KB)
| 1.0 | Dec 2007 | 137 KB | AN-500-1.0 |
AN 499: Mobile SDRAM Interface Using MAX II CPLDs
AN 499 Design Example (450 KB)
| 1.0 | Dec 2007 | 109 KB | AN-499-1.0 |
AN 498: LED Blink Using Auto Stop and Auto Start in MAX II CPLDs
AN 498 Design Example (168 KB)
| 1.0 | Dec 2007 | 104 KB | AN-498-1.0 |
AN 497: LCD Controller Using MAX II CPLDs
AN 497 Design Example (2 MB)
| 1.0 | Dec 2007 | 133 KB | AN-497-1.0 |
AN 496: Using the Internal Oscillator in MAX II CPLDs
AN 496 Design Example (230 KB)
| 1.0 | Dec 2007 | 362 KB | AN-496-1.0 |
AN 495: IDE/ATA Controller Using MAX II CPLDs
AN 495 Design Example (418 KB)
| 1.0 | Dec 2007 | 155 KB | AN-495-1.0 |
AN 494: GPIO Pin Expansion Using I2C Bus Interface in MAX II CPLDs
AN 494 Design Example (273 KB)
| 1.0 | Dec 2007 | 193 KB | AN-494-1.0 |
AN 493: I2C Battery Gauge Interface Using MAX II CPLDs
AN 493 Design Example (465 KB)
| 1.0 | Dec 2007 | 171 KB | AN-493-1.0 |
AN 492: CF+ Interface Using MAX II CPLDs
AN 492 Design Example (346 KB)
| 1.0 | Dec 2007 | 145 KB | AN-492-1.0 |
AN 491: Auto Start Using MAX II CPLDs
AN 491 Design Example (245 KB)
| 1.0 | Dec 2007 | 119 KB | AN-491-1.0 |
AN 490: MAX II CPLDs as Voltage Level Shifters
AN 490 Design Example (147 KB)
| 1.0 | Dec 2007 | 323 KB | AN-490-1.0 |
AN 489: Using the UFM in MAX II Devices
AN 489 Design Example (551 KB)
| 1.0 | Dec 2007 | 161 KB | AN-489-1.0 |
AN 488: Stepper Motor Controller Using MAX II CPLDs
AN 488 Design Example (350 KB)
| 1.0 | Dec 2007 | 100 KB | AN-488-1.0 |
AN 487: SPI to I2S Using MAX II CPLDs
AN 487 Desgin Example (589 KB)
| 1.0 | Dec 2007 | 138 KB | AN-487-1.0 |
AN 486: SPI to I2C Using MAX II CPLDs
AN 486 Design Example (385 KB)
| 1.0 | Dec 2007 | 144 KB | AN-486-1.0 |
AN 485: Serial Peripheral Interface Master in MAX II CPLDs
AN 485 Design Example (305 KB)
| 1.0 | Dec 2007 | 117 KB | AN-485-1.0 |
AN 484: SMBus for GPIO Pin Expansion in MAX II CPLDs
AN 484 Design Example (2 MB)
| 1.0 | Dec 2007 | 120 KB | AN-484-1.0 |
| AN 483: Triple Speed Ethernet Data Path Reference Design | 1.0 | Jan 2008 | 2 MB | AN-483-1.0 |
| AN 480: 1536-Point FFT for 3GPP Long Term Evolution | 1.0 | Oct 2007 | 154 KB | AN-480-1.0 |
| AN 478: Using FPGA-Based Parallel Flash Loader with the Quartus II Software | 1.0 | Nov 2007 | 861 KB | AN-478-1.0 |
| AN477: Designing RGMII Interface with FPGA and HardCopy Devices | 1.0 | Nov 2007 | 261 KB | AN-477-1.0 |
| AN 476: Impact of I/O Settings on Signal Integrity in Stratix III Devices | 1.0 | Oct 2007 | 391 KB | AN-476-1.0 |
| AN 475: Crest Factor Reduction for OFDMA Systems | 1.0 | Dec 2007 | 362 KB | AN-475-1.0 |
| AN 474: Implementing Stratix III Programmable I/O Delay Settings in the Quartus II Software | 1.2 | Mar 2008 | 365 KB | AN-474-1.2 |
AN 473: Using DCFIFO for Data Transfer between Asynchronous Clock Domains
AN473_Design_Example (60 KB)
| 1.0 | Dec 2007 | 1 MB | AN-473-1.0 |
| AN 472: Stratix II GX SSN Design Guidelines | 1.0 | Aug 2007 | 666 KB | AN-472-1.0 |
| AN 470: Best Practices for Incremental Compilation Partitions and Floorplan Assignments | 1.0 | Dec 2007 | 1 MB | AN-470-1.0 |
AN 465: Implementing OCT Calibration in Stratix III Devices
Design Example 1 (200 KB)
Design Example 2 (74 KB)
Design Example 3 (211 KB)
Stratix III OCT Power Up Example (46 KB)
| 1.0 | Nov 2007 | 623 KB | AN-465-1.0 |
| AN 464: DFT/IDFT Reference design | 1.0 | Jun 2007 | 187 KB | AN-464 |
| AN 463: Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs | 1.0 | Jul 2007 | 915 KB | AN-463-1.0 |
| AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III Devices | 1.0 | Jun 2007 | 834 KB | AN-461-1.0 |
AN 459: Guidelines for Developing a Nios II HAL Device Driver
bit_bang_uart.c file (5 KB)
| 1.0 | Aug 2007 | 3 MB | AN-459-1.0 |
AN458: Alternative Nios II Boot Methods
AN458 design example files (30 KB)
Default boot loader sources (17 KB)
| 1.0 | Nov 2007 | 336 KB | AN-458-1.0 |
| AN 457: Integrating Uplink Desubchannelization and Ranging Modules for WiMAX | 1.0 | Feb 2007 | 166 KB | AN-457-1.0 |
AN 456: PCI Express High Performance Reference Design
AN 456 design files (13 MB)
| 1.0 | May 2007 | 613 KB | AN-456-1.0 |
| AN 455: Understanding CIC Compensation Filters | 1.0 | Apr 2007 | 268 KB | AN-455-1.0 |
AN 454: Implementing PLL Reconfiguration in Stratix III Devices
Design Example 1 (364 KB)
Design Example 2 (211 KB)
| 1.1 | Oct 2007 | 543 KB | AN-454-1.1 |
| AN 453: HardCopy II Fitting Techniques | 1.0 | Jun 2007 | 1 MB | AN-453-1.0 |
AN 452: An OFDM Kernel for WiMAX
WiMAX OFDMA Reference Design Web Page (8 KB)
| 1.0 | Feb 2007 | 319 KB | AN-452-1.0 |
| AN 451: Downlink Subchannelization for WiMAX | 1.0 | Feb 2007 | 319 KB | AN-451-1.0 |
| AN 450: Uplink Desubchannelization for WiMAX | 1.0 | Feb 2007 | 319 KB | AN-450-1.0 |
| AN 449: External Memory Interface Design Guidelines for Stratix II, Stratix II GX, and Arria GX Devices | 1.2 | Sep 2007 | 284 KB | AN-449-1.2 |
| AN 448: Stratix III Power Management Design Guide | 1.3 | May 2007 | 201 KB | AN-448-1.3 |
| AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL & LVCMOS I/O Systems | 1.1 | Apr 2008 | 349 KB | AN-447-1.1 |
| AN 444: Dual DIMM DDR2 SDRAM Memory Interface Design Guidelines | 1.0 | Feb 2007 | 7 MB | AN-444-1.0 |
| AN 443: External PHY Support in PCI Express MegaCore Functions | 1.0 | May 2007 | 435 KB | AN-443-1.0 |
| AN 442: Tool Flow for Design of Digital IF for Wireless Systems | 1.0 | May 2007 | 1 MB | AN-442 |
AN 440: Accelerating Nios II Networking Applications
Accelerating Nios II Networking Applications Design (3 MB)
| 1.0 | May 2007 | 193 KB | AN-440-1.0 |
| AN 439: Constellation Mapper and Demapper for WiMAX | 1.1 | May 2007 | 250 KB | AN-439-1.1 |
| AN 438: Constraining and Analyzing Timing for External Memory Interfaces in Stratix III and Cyclone III Devices | 3.0 | Oct 2007 | 306 KB | AN-438-3.0 |
| AN 437: Power Optimization in Stratix III FPGAs | 2.0 | Aug 2007 | 219 KB | AN-437-2.0 |
| AN 436: Design Guidelines for Implementing DDR3 SDRAM Interfaces in Stratix III Devices | 2.0 | Dec 2007 | 1 MB | AN-436-2.0 |
| AN 435: Design Guidelines for Implementing DDR and DDR2 SDRAM Interfaces in Stratix III Devices | 1.0 | Feb 2007 | 1 MB | AN-435-1.0 |
AN 434: Channel Estimation & Equalization for Mobile WiMAX Basestations
Channel Estimation & Equalization Reference Design (8 KB)
| 1.1 | May 2007 | 748 KB | AN-434-1.1 |
| AN 433: Constraining and Analyzing Source-Synchronous Interfaces | 2.0 | Dec 2007 | 1 MB | AN-433-2.0 |
| AN 432: Using Different PLL Settings Between Stratix II and HardCopy II Devices | 1.1 | Dec 2007 | 168 KB | AN-432-1.1 |
| AN 431: PCI Express-to-DDR2 SDRAM Reference Design | 1.0 | Sep 2006 | 2 MB | AN-431-1.0 |
| AN 430: WiMAX OFDMA Ranging | 1.0 | Aug 2006 | 769 KB | AN-430-1.0 |
AN 429: Remote Configuration Over Ethernet with the Nios II Processor
Application Note 429 Design Files (106 KB)
| 1.1 | Nov 2007 | 137 KB | AN-429-1.1 |
| AN 428: MAX II CPLD Design Guidelines | 1.1 | Dec 2007 | 425 KB | AN-428 |
AN 427: Video and Image Processing Up Conversion Example Design
Video Processing Reference Design web page (12 KB)
| 4.0 | Oct 2007 | 2 MB | AN-427-4.0 |
| AN 426: Using MAX II CPLDs as Analog Keyboard Encoders | 1.0 | Jul 2006 | 308 KB | AN-426-1.0 |
| AN 425: Using Command-Line Jam STAPL Solution for Device Programming | 2.0 | Nov 2007 | 496 KB | AN-425-2.0 |
| AN 424: I/O Simulations Using HSPICE | 1.0 | Jun 2006 | 2 MB | AN-424-1.0 |
AN 423: Configuring the MicroBlaster Passive Serial Software Driver
Source Code (150 KB)
| 1.0 | Jun 2006 | 150 KB | AN-423-1.0 |
| AN 422: Power Management in Portable Systems Using MAX II CPLDs | 1.0 | Jul 2006 | 265 KB | AN-422-1.0 |
AN 421: Accelerating WiMAX DUC & DDC System Designs
WiMAX DUC & DDC Reference Design Web Page (9 KB)
| 2.2 | May 2007 | 758 KB | AN-421-2.2 |
AN 417: Accelerating Functions with the C2H Compiler: Scatter-Gather DMA with Checksum
Scatter-Gather DMA Design Files (6 KB)
| 1.1 | Jul 2006 | 424 KB | AN-417-1.1 |
AN 415: DDR and DDR2 SDRAM ECC Reference Design
ECC Reference Design Files (242 bytes)
| 1.0 | Jun 2006 | 291 KB | AN-415 |
AN 414: The JRunner Software Driver: An Embedded Solution for PLD JTAG Configuration
Source Code (221 KB)
| 1.0 | May 2006 | 145 KB | AN-414-1.0 |
| AN 413: Using Legacy Integrated Static Data Path and Controller Megafunction with HardCopy II Structured ASICs | 2.1 | Jul 2007 | 227 KB | AN-413-2.1 |
AN 412: A Scalable OFDMA Engine for WiMAX
WiMAX OFDMA Reference Design Web Page | 2.1 | May 2007 | 359 KB | AN-412-2.1 |
AN 411: Understanding PLL Timing for Stratix II Devices
Design Example 1 (279 KB)
Design Example 2 (233 KB)
| 1.0 | Mar 2006 | 1 MB | AN-411-1.0 |
AN 410: MAX II ISP Update with I/O Control & Register Data Retention
ISP SRAM Download Design Files (11 KB)
| 1.0 | Mar 2006 | 126 KB | AN-410-1.0 |
AN 409: Design Example Using the altlvds Megafunction & the External PLL Option in Stratix II Devices
Design Example (7 MB)
| 1.0 | Mar 2006 | 244 KB | AN-409-1.0 |
| AN 407: Automotive Audio Reference Design | 1.0 | Apr 2006 | 2 MB | AN-407-1.0 |
| AN 404: FFT/IFFT Block Floating Point Scaling | 1.0 | Oct 2005 | 110 KB | AN-404-1.0 |
| AN 403: Avalon Blocks in DSP Builder | 1.0 | Oct 2005 | 483 KB | AN-403-1.0 |
| AN 402: Black-Boxing in DSP Builder | 1.0 | Oct 2005 | 242 KB | AN-402-1.0 |
AN 400: SMBus Interface for the User Flash Memory in MAX II Devices
SMBus (Read/Write/Erase) Design Files (8 KB)
SMBus (Read Only) Design Files (8 KB)
| 1.0 | Sep 2005 | 1 MB | AN-400-1.0 |
| AN 398: Using DDR/DDR2 SDRAM With SOPC Builder | 1.1 | Aug 2006 | 775 KB | AN-398-1.1 |
AN 397: Interfacing to External Processors
Design Files (13 KB)
| 1.0 | Aug 2005 | 363 KB | AN-397-1.0 |
| AN 396: Crest Factor Reduction | 1.0 | Jun 2007 | 1 MB | AN-396 |
| AN 395: Stratix II Professional FFT Co-Processor Reference Design | 1.0 | Aug 2005 | 446 KB | AN-395-1.0 |
| AN 394: Using SOPC Builder & DSP Builder Tool Flow | 1.0 | Aug 2005 | 910 KB | AN-394-1.0 |
| AN 393: Stratix II Professional Filtering Lab | 1.0 | Aug 2005 | 1 MB | AN-393-1.0 |
AN 392: Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces
three controller example (26 KB)
two controller example (15 KB)
| 2.0 | Jul 2007 | 306 KB | AN-392-2.0 |
AN 391: Profiling Nios II Systems
AN 391: Performance Checksum Design Files (7 KB)
AN 391: Profiler Checksum Design Files (4 KB)
| 1.2 | Feb 2006 | 784 KB | AN-391-1.2 |
| AN 390: PCI-to-DDR2 SDRAM Reference Design | 1.0 | Sep 2005 | 261 KB | AN-390-1.0 |
| AN 388: High-Performance EMIF Bridge Core | 1.2 | Sep 2005 | 435 KB | AN-388 |
| AN 387: Upgrading a FIR Compiler v3.1.x Design to v3.2.x | 1.0 | May 2005 | 537 KB | AN-387-1.0 |
| AN 385: Using Stratix GX Transceivers for PCI Express | 1.0 | Jun 2005 | 4 MB | AN-385-1.0 |
AN 384: Using Calibrated Series On-Chip Termination in Stratix II Devices
User-Mode Calibration Reference Design (Quartus II Version 4.2 SP1) (233 KB)
User-Mode Calibration Reference Design (Quartus II Version 5.0) (233 KB)
| 1.0 | Apr 2005 | 116 KB | AN-384-1.0 |
| AN 383: Cyclone II DDR2 SDRAM Demonstration | 1.0 | Apr 2005 | 175 KB | AN-383-1.0 |
| AN 382: Using Stratix GX Transceivers for CPRI | 1.0 | May 2005 | 953 KB | AN-382-1.0 |
| AN 380: Test DDR or DDR2 SDRAM Interfaces on Hardware Using the Example Driver | 1.2 | Jun 2006 | 630 KB | AN-380-1.2 |
AN 379: Active Serial Memory Interface Controller Reference Design
Design Files (11 KB)
| 1.0 | Mar 2005 | 191 KB | AN-379-1.0 |
| AN 377: Edge Detection Using SOPC Builder & DSP Builder Tool Flow | 1.0 | May 2005 | 1 MB | AN-377-1.0 |
| AN 376: Cyclone II Filtering Lab | 1.0 | May 2005 | 1 MB | AN-376-1.0 |
| AN 375: Cyclone II FFT Co-Processor Reference Design | 1.0 | May 2005 | 566 KB | AN-375-1.0 |
AN 374: Video Over IP Reference Design
Video Over IP Reference Design Web Page (9 KB)
| 2.5 | Jan 2008 | 667 KB | AN-374-2.5 |
| AN 373: Avalon Video Input Module | 1.0 | Dec 2004 | 154 KB | AN-373 |
| AN 372: Avalon LCD Controller | 1.0 | Dec 2004 | 159 KB | AN-372 |
| AN 371: Automotive Graphics System Reference Design | 1.0 | Dec 2004 | 195 KB | AN-371 |
| AN 370: Using the Serial FlashLoader With the Quartus II Software | 3.0 | Jul 2006 | 792 KB | AN-370-3.0 |
AN 369: AES3/EBU Reference Design
AES3/EBU Reference Design Web Page (10 KB)
| 1.1 | Feb 2005 | 1 MB | AN-369 |
AN 367: Implementing PLL Reconfiguration in Stratix II Devices
Example 1: altpll_reconfig Design with the MIF (244 KB)
Example 2: altpll_reconfig Design with Write Parameters (249 KB)
Example 3: altpll_reconfig Design for Phase Shift Stepping (251 KB)
| 2.0 | Dec 2005 | 690 KB | AN-367-2.0 |
| AN 366: Understanding I/O Output Timing for Altera Devices | 1.0 | Jul 2006 | 311 KB | AN-366-1.0 |
| AN 364: Edge Detection Reference Design | 1.0 | Oct 2004 | 1 MB | AN-364-1.0 |
| AN 363: FFT Co-Processor Reference Design | 1.0 | Oct 2004 | 1 MB | AN-363-1.0 |
| AN 362: Stratix II Filtering Lab | 1.0 | Oct 2004 | 1 MB | AN-362-1.0 |
| AN 361: Interfacing DDR & DDR2 SDRAM With Cyclone II Devices | 1.3 | Jun 2006 | 380 KB | AN-361-1.3 |
| AN 360: Updating Simulation Models for the POS-PHY Level 4 MegaCore Function | 1.1 | Dec 2004 | 63 KB | AN-360-1.1 |
| AN 359: POS-PHY Level 4 MegaCore Function Parameter Selection Calculator | 1.0 | Jul 2004 | 219 KB | AN-359-1.0 |
| AN 358: Thermal Management for FPGAs | 1.1 | Feb 2007 | 157 KB | AN-358-1.1 |
| AN 357: Error Detection & Recovery Using CRC in Altera FPGA Devices | 1.3 | Feb 2007 | 179 KB | AN-357-1.3 |
| AN 355: Stratix II Device System Power Considerations | 1.0 | Jun 2004 | 274 KB | AN-355-1.0 |
| AN 353: Reflow Soldering Guidelines for Lead-Free Packages | 1.0 | Jul 2004 | 89 KB | AN-353-1.0 |
| AN 352: FPGA Peripheral Expansion & FPGA Co-Processing | 1.0 | Jul 2004 | 552 KB | AN352-1.0 |
| AN 351: Simulating Nios II Embedded Processor Designs | 1.1 | Nov 2007 | 1 MB | AN-351-1.1 |
| AN 350: Upgrading Nios Processor Systems to the Nios II Processor | 1.1 | Jul 2006 | 617 KB | AN-350-1.1 |
| AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices | 1.0 | May 2004 | 280 KB | AN-349-1.0 |
| AN 348: Interfacing DDR SDRAM with Cyclone Devices | 1.1 | Jul 2004 | 441 KB | AN-348-1.1 |
| AN 347: Farrow-Based Decimating Sample Rate Converter | 1.0 | Mar 2004 | 256 KB | AN-347-1.0 |
| AN 346: Using the Nios Development Board Configuration Controller Reference Designs | 1.1 | Aug 2006 | 307 KB | AN-346-1.1 |
| AN 345: Altera Design Flow for Lattice Semiconductor Users | 1.1 | Jan 2005 | 581 KB | AN-345-1.1 |
| AN 344: ASI Demonstration | 2.0 | Oct 2006 | 145 KB | AN-344-2.0 |
| AN 343: OpenCore Evaluation of AMPP Megafunctions | 1.0 | Feb 2004 | 294 KB | AN-343-1.0 |
| AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices | 2.0 | Dec 2005 | 428 KB | AN-342-2.0 |
| AN 341: Using the Design Security Feature in Stratix II and Stratix II GX Devices | 2.1 | Aug 2007 | 1 MB | AN-341-2.1 |
| AN 339: Serial Digital Interface Demonstration for Stratix II GX Devices | 3.3 | May 2007 | 288 KB | AN-339 |
| AN 336: Using External Series and Parallel Termination with Stratix and Stratix GX Devices | 1.0 | Nov 2003 | 1 MB | AN-336-1.0 |
| AN 335: POS-PHY Level 4 MegaCore Function v2.1.0 Wrapper Features | 1.0 | Jan 2004 | 282 KB | AN-335-1.0 |
| AN 334: ADI Parallel Port SDRAM Controller Reference Design | 1.3 | Jun 2005 | 753 KB | AN-334-1.3 |
AN 333: Developing Peripherals for SOPC Builder
Slave Peripheral Design Files (455 KB)
Streaming Slave 1C20 Design Files (1 MB)
Streaming Slave 1S10 Design Files (1 MB)
Streaming Slave 1S10ES Design Files (1 MB)
Streaming Slave 1S40 Design Files (1 MB)
| 1.0 | Apr 2004 | 267 KB | AN-333-1.0 |
| AN 332: Link-Port Reference Design | 1.3 | Feb 2005 | 1 MB | AN-332 |
| AN 330: Connecting Altera 3.3-V PCI devices to a 5-V PCI Bus | 1.0 | Feb 2004 | 112 KB | AN-330-1.0 |
|
文档资料
> 
