资料：应用手册

Note: Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Title	Doc Version	Release Date	File Size	Document Part Number
Application Notes
AN 605: Using the EyeQ Feature in Stratix IV Transceivers      Stratix IV GX Board EyeQ Reference Design (1 MB)	1.0	Mar 2010	962 KB	AN-605-1.0
AN 601: Serial Digital Interface Reference Design for Arria II GX Devices      Design Files for AN 601 (3 MB)	1.1	Feb 2010	582 KB	AN-601-1.1
AN 597: Getting Started Flow for Board Designs	1.1	Mar 2010	161 KB	AN-597-1.1
AN 592: Cyclone IV Design Guidelines	1.1	Jan 2010	392 KB	AN-592-1.1
AN 580: Achieving Timing Closure in Basic (PMA Direct) Functional Mode      AN580_scripts.zip (17 KB)	2.0	Feb 2010	423 KB	AN-580-2.0
AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices	2.1	Jan 2010	3 MB	AN-558-2.1
AN 554: How to Read HardCopy PrimeTime Timing Reports	2.0	Mar 2010	554 KB	AN-554-2.0
AN 550: Using the DLL Phase Offset Feature in Stratix FPGAs and HardCopy ASICs      altmemphy_ext_dll.zip (48 KB)      altmemphy_int_dll.zip (47 KB)      static_dll.zip (18 KB)	2.0	Mar 2010	547 KB	AN-550-2.0
AN 540: Nios II MPU Usage      Design Files for AN 540 (221 KB)	1.0	Mar 2010	385 KB	AN540-1.0
AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III and Stratix IV Devices      Design Example for AN 461 (3 MB)	1.2	Feb 2010	986 KB	AN-461-1.2
AN 459: Guidelines for Developing a Nios II HAL Device Driver      AN 459 Design Example (52 KB)	3.0	Jan 2010	964 KB	AN-459-3.0
AN 433: Constraining and Analyzing Source-Synchronous Interfaces	2.2	Mar 2010	2 MB	AN-433-2.2
AN 432: Using Different PLL Settings Between Stratix II and HardCopy II Devices	1.2	Mar 2010	149 KB	AN-432-1.2
AN 431: PCI Express to External Memory Reference Design	1.3	Feb 2010	408 KB	AN-431-1.3
AN 600: Serial Digital Interface Reference Design for Stratix IV Devices      Design Files for AN 600 (1 MB)	1.0	Dec 2009	586 KB	AN-600-1.0
AN599: Arria II GX RapidIO Interoperability with TI 6488 DSP Reference Design	1.0	Dec 2009	1,019 KB	AN-599-1.0
AN 595: Vectored Interrupt Controller Usage and Applications      Example Designs for AN595 (503 KB)	1.0	Nov 2009	246 KB	AN595-1.0
AN 593: Anti-Tamper Protection for Cyclone III LS Devices	1.0	Oct 2009	626 KB	AN-593-1.0
AN 589: Using the Design Security Feature in Cyclone III LS Devices	1.0	Sep 2009	1 MB	AN-589-1.0
AN 588: 10-Gbps Ethernet Hardware Demonstration Reference Design	1.1	Dec 2009	1 MB	AN-588-1.1
AN587: DPRIO and Multiple Instances SDI Application	1.0	Aug 2009	1,002 KB	AN-587-1.0
AN 586: Porting the Jam STAPL and Jam STAPL Byte-Code Players to an Embedded System	1.0	Aug 2009	176 KB	AN-586-1.0
AN585: Simulation Debugging Using Triple Speed Ethernet Testbench      AN585: Test Cases (3 MB)	1.0	Aug 2009	368 KB	AN-585-1.0
AN 584: Timing Closure Methodology for Advanced FPGA Designs      AN 584: Design Examples (380 KB)	1.0	Aug 2009	1 MB	AN-584-1.0
AN 583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs      AN 583: VCC to VCCDPLL Spice Examples (159 KB)	1.0	Jul 2009	889 KB	AN-583-1.0
AN 581: High Definition Video Reference Design (V2)	1.0	Nov 2009	1 MB	AN-581-1.0
AN 578: Manual Placement of CMU PLLs and ATX PLLs in Stratix IV GX and GT Devices	1.0	May 2009	1 MB	AN-578-1.0
AN 577: Recommended Protocol Configurations for Stratix IV GX FPGAs	2.0	Dec 2009	753 KB	AN-577-2.0
AN 574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology	1.0	May 2009	899 KB	AN-574-1.0
AN 573: Implementing the Interlaken Protocol in Stratix IV Transceivers (Not applicable when designing with Stratix IV GX and Stratix IV GT engineering sample devices)	1.1	Dec 2009	768 KB	AN-573-1.1
AN 572: Implementing the Scalable SERDES Framer Interface (SFI-S) Protocol in Stratix IV GT Devices (Not applicable when designing with Stratix IV GT engineering sample devices)	2.0	Jan 2010	284 KB	AN-572-2.0
AN 571: Implementing the SERDES Framer Interface Level 5 (SFI-5.1) Protocol in Stratix IV Devices	1.0	Jun 2009	549 KB	AN-571-1.0
AN 570: Implementing the 40G/100G Ethernet Protocol in Stratix IV Devices (Not applicable when designing with Stratix IV GT engineering sample devices)	1.1	Dec 2009	1 MB	AN-570-1.1
AN 569: SDI Flywheel Video Decoder Reference Design	1.0	May 2009	1 MB	AN-569-1.0
RapidIO Interoperability with TI 6488 DSP Reference Design (AN568: RapidIO Interoperability with TI 6488 DSP Reference Design)	1.0	May 2009	883 KB	AN568-1.0
AN 567: Quartus II Design Separation Flow	1.0	Jun 2009	3 MB	AN-567-1.0
AN 563: Arria II GX Design Guidelines	1.0	Feb 2009	752 KB	AN-563-1.0
AN561: Stratix II GX 10GbE Loopback Reference Design	1.1	Oct 2009	549 KB	AN-561-1.1
AN 559: High Definition Video Reference Design (V1)	1.0	Dec 2008	1 MB	AN-559-1.0
AN557: Stratix III to Stratix IV E Cross-Family Migration Guidelines	2.0	Sep 2009	924 KB	AN-557-2.0
AN556: Using the Design Security Feature in Arria II GX and Stratix IV Devices	1.1	Jun 2009	1 MB	AN-556-1.1
AN 553: Debugging Transceivers      AN 553: Design Files (874 KB)	1.1	Dec 2009	1 MB	AN-553-1.1
AN 551: SDI-ASI Auto Detect Reference Design for Stratix II GX Devices	1.0	Nov 2008	232 KB	AN-551-1.0
AN 549: Managing Designs with Multiple FPGAs	1.0	Sep 2008	776 KB	AN-549-1.0
AN 548: Nios II Compact Configuration System for Cyclone III      Design Files for AN 548 (597 KB)	1.0	Nov 2008	320 KB	AN-548-1.0
AN 547: Putting the MAX II CPLD in Hibernation Mode to Achieve Zero Standby Current      MAX II Hibernation Design (87 KB)	1.0	Jan 2009	256 KB	AN-547-1.0
AN 545: Design Guidelines and Timing Closure Techniques for HardCopy ASICs      Example_design.zip (578 KB)	2.0	Dec 2009	2 MB	AN-545-2.0
AN 544: Digital IF Modem Design with the DSP Builder Advanced Blockset	1.0	Aug 2008	976 KB	AN-544-1.0
AN543: Debugging Nios II Software Using the Lauterbach Debugger      Example Design for AN543 (6 MB)	1.0	Apr 2009	278 KB	AN543-1.0
AN 542: High Definition Video Monitoring Reference Design (M5)	1.2	Nov 2008	814 KB	AN-542-1.2
AN 541: SerialLite II Hardware Debugging Guide	1.0	Aug 2008	1 MB	AN-541-1.0
AN539: Test Methodology of Error Detection and Recovery using CRC in Altera FPGA Devices      AN539 Design Example (425 KB)	1.1	Jan 2009	406 KB	AN-539-1.1
AN 537: Implementing UNH-IOL Test Suite Compliance in Arria GX and Stratix II GX Gigabit Ethernet Designs      carrier_detect_logic.zip (2 KB)	1.0	Sep 2008	514 KB	AN-537-1.0
AN 536: Design Guidelines for Preparing HardCopy II ASICs	1.0	Sep 2008	1 MB	AN-536-1.0
AN 533:Automotive Information and Entertainment Reference Designs	1.3	Nov 2009	3 MB	AN-533-1.3
AN 532: An SOPC Builder PCI Express Design with GUI Interface      Design Files for AN 532 (5 MB)	1.0	Jun 2008	285 KB	AN-532-1.0
AN 531: Reducing Power with Hardware Accelerators      Design Files for AN 531 (1 MB)	1.0	May 2008	151 KB	AN-531-1.0
AN 530: Optimizing Impedence Discontinuity Caused by Surface Mount Pads for High-Speed Channel Designs	1.0	May 2008	208 KB	AN-530-1.0
AN 529: Via Optimization Techniques for High-Speed Channel Designs	1.0	May 2008	690 KB	AN-529-1.0
AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing	1.0	May 2008	1 MB	AN-528-1.0
AN527: Implementing an LCD Controller	1.0	May 2008	344 KB	AN-527-1.0
AN 526: 3GPP UMTS Turbo Reference Design	2.0	Jan 2010	374 KB	AN-526-2.0
AN 524: High Definition Video Monitoring Reference Design (M4)	1.0	Apr 2008	567 KB	AN-524-1.0
AN523: Cyclone III Configuration Interface Guidelines with EPCS Devices	1.1	Jun 2009	966 KB	AN-523-1.1
AN 522: Implementing Bus LVDS Interface in Supported Altera Device Families      Design Examples for AN 522 (37 KB)	2.0	Nov 2009	856 KB	AN-522-2.0
AN 521: Cyclone III Active Parallel Remote System Upgrade Reference Design      AN521 Design Files (1 MB)	1.1	Aug 2009	994 KB	AN-521-1.1
AN 520: DDR3 SDRAM Memory Interface Termination and Layout Guidelines	1.1	May 2009	909 KB	AN-520-1.1
AN 519: Stratix IV Design Guidelines	1.1	May 2009	493 KB	AN-519-1.1
AN 518: SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices	1.0	May 2008	1 MB	AN-518-1.0
AN 517: Using High-Performance DDR, DDR2, DDR3 SDRAM with SOPC Builder      AN 517 Design Files (2 MB)	1.0	Apr 2008	1 MB	AN-517-1.0
AN 515: 24K FFT for 3GPP LTE RACH Detection	1.0	Nov 2008	230 KB	AN-515-1.0
AN 514: Power Optimization in Stratix IV FPGAs	1.0	May 2008	221 KB	AN-514-1.0
AN 513: RapidIO Interoperability With TI 6482 DSP Reference Design	2.0	Nov 2008	867 KB	AN-513-2.0
AN 512: Using the Design Security Feature in Stratix III Devices	1.1	Mar 2009	1 MB	AN-512-1.1
AN 511: Polyphase Modulation Using a FPGA for High-Speed Applications	1.0	Feb 2008	279 KB	AN-511-1.0
AN 509: Multiplexing SDIO Devices Using MAX II CPLDs      AN 509 Design Example (721 KB)	1.0	Dec 2007	198 KB	AN-509-1.0
AN 508: Cyclone III Simultaneous Switching Noise (SSN) Design Guidelines	1.0	Dec 2007	379 KB	AN-508-1.0
AN 507: Implementing PLL Reconfiguration in Cyclone III Devices      Design Example 1: an507_de1_display.zip (204 KB)      Design Example 2: an507_de2_dynphase.zip (84 KB)	1.0	Jan 2008	739 KB	AN-507-1.0
AN 506: QR Matrix Decomposition	2.0	Mar 2008	371 KB	AN-506-2.0
AN 505: 3GPP LTE Turbo Reference Design	2.0	Jan 2010	388 KB	AN-505-2.0
AN 504: DSP System Design in Stratix III Devices      Design Example 1: Parallel FIR (79 KB)      Design Example 2: Multi-Channel FIR (20 KB)      Design Example 3: MAC_FIR (vhdl) (21 KB)      Design Example 4: Large Mult_Add (11 KB)	1.0	Feb 2008	1 MB	AN-504-1.0
AN 503: Implementing OFDM Modulation for Wireless Communications	1.0	Jan 2008	268 KB	AN-503-1.0
AN 502: Implementing an SMBus Controller in MAX II CPLDs      AN 502 Design Example (2 MB)	1.0	Dec 2007	129 KB	AN-502-1.0
AN 501: Pulse Width Modulation Using MAX II CPLDs      AN 501 Design Example (279 KB)	1.0	Dec 2007	104 KB	AN-501-1.0
AN 500: NAND Flash Memory Interface with MAX II CPLDs      AN 500 Design Example (187 KB)	1.0	Dec 2007	137 KB	AN-500-1.0
AN 499: Mobile SDRAM Interface Using MAX II CPLDs      AN 499 Design Example (450 KB)	1.0	Dec 2007	109 KB	AN-499-1.0
AN 498: LED Blink Using Auto Stop and Auto Start in MAX II CPLDs      AN 498 Design Example (168 KB)	1.0	Dec 2007	104 KB	AN-498-1.0
AN 497: LCD Controller Using MAX II CPLDs      AN 497 Design Example (2 MB)	1.0	Dec 2007	133 KB	AN-497-1.0
AN 496: Using the Internal Oscillator in MAX II CPLDs      AN 496 Design Example (230 KB)	1.0	Dec 2007	362 KB	AN-496-1.0
AN 495: IDE/ATA Controller Using MAX II CPLDs      AN 495 Design Example (418 KB)	1.0	Dec 2007	155 KB	AN-495-1.0
AN 494: GPIO Pin Expansion Using I2C Bus Interface in MAX II CPLDs      AN 494 Design Example (273 KB)	1.0	Dec 2007	193 KB	AN-494-1.0
AN 493: I2C Battery Gauge Interface Using MAX II CPLDs      AN 493 Design Example (465 KB)	1.0	Dec 2007	171 KB	AN-493-1.0
AN 492: CF+ Interface Using MAX II CPLDs      AN 492 Design Example (346 KB)	1.0	Dec 2007	145 KB	AN-492-1.0
AN 491: Auto Start Using MAX II CPLDs      AN 491 Design Example (245 KB)	1.0	Dec 2007	119 KB	AN-491-1.0
AN 490: MAX II CPLDs as Voltage Level Shifters      AN 490 Design Example (147 KB)	1.0	Dec 2007	323 KB	AN-490-1.0
AN 489: Using the UFM in MAX II Devices      AN 489 Design Example (551 KB)	1.0	Dec 2007	161 KB	AN-489-1.0
AN 488: Stepper Motor Controller Using MAX II CPLDs      AN 488 Design Example (350 KB)	1.0	Dec 2007	100 KB	AN-488-1.0
AN 487: SPI to I2S Using MAX II CPLDs      AN 487 Desgin Example (589 KB)	1.0	Dec 2007	138 KB	AN-487-1.0
AN 486: SPI to I2C Using MAX II CPLDs      AN 486 Design Example (385 KB)	1.0	Dec 2007	144 KB	AN-486-1.0
AN 485: Serial Peripheral Interface Master in MAX II CPLDs      AN 485 Design Example (305 KB)	1.0	Dec 2007	117 KB	AN-485-1.0
AN 484: SMBus for GPIO Pin Expansion in MAX II CPLDs      AN 484 Design Example (2 MB)	1.0	Dec 2007	120 KB	AN-484-1.0
AN 483: Triple Speed Ethernet Data Path Reference Design	1.1	Jun 2009	2 MB	AN-483-1.1
AN 482: High Definition Video Monitoring Reference Design (M2)	4.0	Aug 2008	621 KB	AN-482-4.0
AN 481: Applying Multicycle Exceptions in the TimeQuest Timing Analyzer	1.0	Jul 2008	2 MB	AN-481-1.0
AN 480: 1536-Point FFT for 3GPP Long Term Evolution	1.0	Oct 2007	154 KB	AN-480-1.0
AN 479: Design Guidelines for Implementing LVDS Interfaces in Cyclone Series Devices	1.1	Jun 2009	435 KB	AN-479-1.1
AN 478: Using FPGA-Based Parallel Flash Loader with the Quartus II Software	1.0	Nov 2007	861 KB	AN-478-1.0
AN 477: Designing RGMII Interface with FPGA and HardCopy Devices	2.0	Jan 2010	519 KB	AN-477-1.0
AN 476: Impact of I/O Settings on Signal Integrity in Stratix III Devices	1.0	Oct 2007	391 KB	AN-476-1.0
AN 475: Crest Factor Reduction for OFDMA Systems	1.0	Dec 2007	362 KB	AN-475-1.0
AN 474: Implementing Stratix III Programmable I/O Delay Settings in the Quartus II Software	1.2	Mar 2008	365 KB	AN-474-1.2
AN 472: Stratix II GX SSN Design Guidelines	1.0	Aug 2007	666 KB	AN-472-1.0
AN 471: High-Performance FPGA PLL Analysis with TimeQuest	1.0	Aug 2007	227 KB	AN-471-1.0
AN 469: Stratix III Design Guidelines	1.1	May 2008	628 KB	AN-469-1.1
AN 466: Cyclone III Design Guidelines	1.2	Nov 2008	1 MB	AN-466-1.2
AN 465: Implementing OCT Calibration in Stratix III Devices      Design Example 1 (200 KB)      Design Example 2 (74 KB)      Design Example 3 (211 KB)      Stratix III OCT Power Up Example (46 KB)	1.0	Nov 2007	623 KB	AN-465-1.0
AN 464: DFT/IDFT Reference design	1.0	Jun 2007	187 KB	AN-464
AN 463: Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs	1.0	Jul 2007	915 KB	AN-463-1.0
AN 462: Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction      Example Design for AN 462: top.qar (715 KB)	1.3	Apr 2009	784 KB	AN-462-1.3
AN458: Alternative Nios II Boot Methods      AN458 design example files (37 KB)	1.1	Sep 2008	334 KB	AN-458-1.1
AN 457: Integrating Uplink Desubchannelization and Ranging Modules for WiMAX	1.0	Feb 2007	166 KB	AN-457-1.0
AN 456: PCI Express High Performance Reference Design	1.2	Aug 2009	379 KB	AN-456-1.2
AN 455: Understanding CIC Compensation Filters	1.0	Apr 2007	268 KB	AN-455-1.0
AN 454: Implementing PLL Reconfiguration in Stratix III and Stratix IV Devices      Design Examples 1 (412 KB)      Design Examples 2 (236 KB)	2.0	Dec 2009	868 KB	AN-454-2.0
AN 453: HardCopy II Fitting Techniques	2.0	Nov 2008	716 KB	AN-453-2.0
AN 452: An OFDM Kernel for WiMAX      WiMAX OFDMA Reference Design Web Page (8 KB)	1.0	Feb 2007	319 KB	AN-452-1.0
AN 451: Downlink Subchannelization for WiMAX	1.0	Feb 2007	319 KB	AN-451-1.0
AN 450: Uplink Desubchannelization for WiMAX	1.0	Feb 2007	319 KB	AN-450-1.0
AN 449: External Memory Interface Design Guidelines for Stratix II, Stratix II GX, and Arria GX Devices	1.2	Sep 2007	284 KB	AN-449-1.2
AN 448: Stratix III Power Management Design Guide	1.3	May 2007	201 KB	AN-448-1.3
AN 447: Interfacing Cyclone III and Cyclone IV Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems	2.0	Nov 2009	396 KB	AN-447-2.0
AN 446: Debugging Nios II Systems with the SignalTap II Embedded Logic Analyzer      signal_tap_test software file (4 KB)	1.2	Jun 2008	257 KB	AN-446-1.2
AN 445: Design Guidelines for Implementing DDR and DDR2 SDRAM Interfaces in Cyclone III Devices      AN 445 Design Example (572 KB)	2.2	Jun 2009	2 MB	AN-445-2.2
AN 444: Dual DIMM DDR2 SDRAM Interface Design Guidelines	1.1	May 2009	7 MB	AN-444-1.1
AN 443: External PHY Support in PCI Express MegaCore Functions	1.0	May 2007	435 KB	AN-443-1.0
AN 442: Tool Flow for Design of Digital IF for Wireless Systems	1.0	May 2007	1 MB	AN-442
AN 440: Accelerating Nios II Networking Applications      Accelerating Nios II Networking Applications Design (3 MB)	1.1	Jun 2009	179 KB	AN-440-1.1
AN 439: Constellation Mapper and Demapper for WiMAX	1.1	May 2007	250 KB	AN-439-1.1
AN 438: Constraining and Analyzing Timing for External Memory Interfaces in Stratix IV, Stratix III, Arria II GX, and Cyclone III Devices      SIII_phase_shift (5 KB)	4.1	May 2009	976 KB	AN-438-4.1
AN 437: Power Optimization in Stratix III FPGAs	2.0	Aug 2007	219 KB	AN-437-2.0
AN 436: Using DDR3 SDRAM with Stratix III and Stratix IV Devices      AN 436 Design Files (11 MB)	4.0	Nov 2008	2 MB	AN-436-4.0
AN 435: Using DDR and DDR2 SDRAM with Stratix III and Stratix IV Devices      AN 435 Design Files (3 MB)	2.0	Aug 2008	2 MB	AN-435-2.0
AN 434: Channel Estimation & Equalization for Mobile WiMAX Basestations      Channel Estimation & Equalization Reference Design (8 KB)	1.1	May 2007	748 KB	AN-434-1.1
AN 430: WiMAX OFDMA Ranging	1.0	Aug 2006	769 KB	AN-430-1.0
AN 429: Remote Configuration Over Ethernet with the Nios II Processor      Application Note 429 Design Files (3 MB)	2.0	Mar 2009	207 KB	AN-429-2.0
AN 428: MAX II CPLD Design Guidelines	1.1	Dec 2007	425 KB	AN-428
AN 427: Video and Image Processing Example Design      Video Processing Reference Design web page (12 KB)	8.0	Nov 2009	3 MB	AN-427-8.0
AN 426: Using MAX II CPLDs as Analog Keyboard Encoders	1.0	Jul 2006	308 KB	AN-426-1.0
AN 425: Using Command-Line Jam STAPL Solution for Device Programming	3.0	Jul 2009	302 KB	AN-425-3.0
AN 424: I/O Simulations Using HSPICE	1.0	Jun 2006	2 MB	AN-424-1.0
AN 423: Configuring the MicroBlaster Passive Serial Software Driver      Source Code (149 KB)	1.1	Jun 2008	211 KB	AN-423-1.1
AN 422: Power Management in Portable Systems Using MAX II CPLDs	1.0	Jul 2006	265 KB	AN-422-1.0
AN 421: Accelerating WiMAX DUC & DDC System Designs      WiMAX DUC & DDC Reference Design Web Page (9 KB)	2.2	May 2007	758 KB	AN-421-2.2
AN 418: SRunner: An Embedded Solution for Serial Configuration Device Programming      Source Code (254 KB)	1.1	Jun 2008	288 KB	AN-418-1.1
AN 417: Accelerating Functions with the C2H Compiler: Scatter-Gather DMA with Checksum      Scatter-Gather DMA Design Files (6 KB)	1.1	Jul 2006	424 KB	AN-417-1.1
AN 415: DDR and DDR2 SDRAM ECC Reference Design      ECC Reference Design Files (242 bytes)	1.0	Jun 2006	291 KB	AN-415
AN 414: The JRunner Software Driver: An Embedded Solution for PLD JTAG Configuration      Source Code (221 KB)	1.0	May 2006	145 KB	AN-414-1.0
AN 413: Using Legacy Integrated Static Data Path and Controller Megafunction with HardCopy II Structured ASICs	2.1	Jul 2007	227 KB	AN-413-2.1
AN 412: A Scalable OFDMA Engine for WiMAX      WiMAX OFDMA Reference Design Web Page	2.1	May 2007	359 KB	AN-412-2.1
AN 411: Understanding PLL Timing for Stratix II Devices      Design Example 1 (279 KB)      Design Example 2 (233 KB)	1.0	Mar 2006	1 MB	AN-411-1.0
AN 410: MAX II ISP Update with I/O Control & Register Data Retention      ISP SRAM Download Design Files (11 KB)	1.0	Mar 2006	126 KB	AN-410-1.0
AN 409: Design Example Using the altlvds Megafunction & the External PLL Option in Stratix II Devices      Design Example (7 MB)	1.0	Mar 2006	244 KB	AN-409-1.0
AN 408: DDR2 Memory Interface Termination, Drive Strength, Loading, and Design Layout Guidelines      SII Simulation Example (3 KB)      SIII Simulation Example (3 KB)	2.1	Jul 2008	4 MB	AN-408-2.1
AN 407: Automotive Audio Reference Design	1.0	Apr 2006	2 MB	AN-407-1.0
AN 404: FFT/IFFT Block Floating Point Scaling	1.0	Oct 2005	110 KB	AN-404-1.0
AN 400: SMBus Interface for the User Flash Memory in MAX II Devices      SMBus (Read/Write/Erase) Design Files (8 KB)      SMBus (Read Only) Design Files (8 KB)	1.0	Sep 2005	1 MB	AN-400-1.0
AN 398: Using DDR/DDR2 SDRAM With SOPC Builder	1.1	Aug 2006	775 KB	AN-398-1.1
AN 396: Crest Factor Reduction	1.0	Jun 2007	1 MB	AN-396
AN 395: Stratix II Professional FFT Co-Processor Reference Design	1.0	Aug 2005	446 KB	AN-395-1.0
AN 393: Stratix II Professional Filtering Lab	1.0	Aug 2005	1 MB	AN-393-1.0
AN 392: Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces      three controller example (26 KB)      two controller example (15 KB)	2.0	Jul 2007	306 KB	AN-392-2.0
AN 391: Profiling Nios II Systems      AN 391 Profiler Example Files (15 KB)	1.3	Jul 2008	406 KB	AN-391-1.3
AN 388: High-Performance EMIF Bridge Core	1.2	Sep 2005	435 KB	AN-388
AN 387: Upgrading a FIR Compiler v3.1.x Design to v3.2.x	1.0	May 2005	537 KB	AN-387-1.0
AN 386: Using the Parallel Flash Loader with the Quartus II Software      Flash Memory (873 bytes)      Nios Design (567 KB)	5.0	Dec 2009	2 MB	AN-386-5.0
AN 385: Using Stratix GX Transceivers for PCI Express	1.0	Jun 2005	4 MB	AN-385-1.0
AN 384: Using Calibrated Series On-Chip Termination in Stratix II Devices      User-Mode Calibration Reference Design (Quartus II Version 4.2 SP1) (233 KB)      User-Mode Calibration Reference Design (Quartus II Version 5.0) (233 KB)	1.0	Apr 2005	116 KB	AN-384-1.0
AN 383: Cyclone II DDR2 SDRAM Demonstration	1.0	Apr 2005	175 KB	AN-383-1.0
AN 380: Test DDR or DDR2 SDRAM Interfaces on Hardware Using the Example Driver	1.2	Jun 2006	630 KB	AN-380-1.2
AN 379: Active Serial Memory Interface Controller Reference Design      Design Files (11 KB)	1.0	Mar 2005	191 KB	AN-379-1.0
AN 376: Cyclone II Filtering Lab	1.0	May 2005	1 MB	AN-376-1.0
AN 375: Cyclone II FFT Co-Processor Reference Design	1.0	May 2005	566 KB	AN-375-1.0
AN 373: Avalon Video Input Module	1.0	Dec 2004	154 KB	AN-373
AN 372: Avalon LCD Controller	1.0	Dec 2004	159 KB	AN-372
AN 371: Automotive Graphics System Reference Design	1.0	Dec 2004	195 KB	AN-371
AN 370: Using the Serial FlashLoader With the Quartus II Software	3.1	Apr 2009	1 MB	AN-370-3.1
AN 369: AES3/EBU Reference Design      AES3/EBU Reference Design Web Page (10 KB)	1.1	Feb 2005	1 MB	AN-369
AN 367: Implementing PLL Reconfiguration in Stratix II Devices      Example 1: altpll_reconfig Design with the MIF (244 KB)      Example 2: altpll_reconfig Design with Write Parameters (249 KB)      Example 3: altpll_reconfig Design for Phase Shift Stepping (251 KB)	2.1	May 2009	717 KB	AN-367-2.1
AN 366: Understanding I/O Output Timing for Altera Devices	1.0	Jul 2006	311 KB	AN-366-1.0
AN 364: Edge Detection Reference Design	1.0	Oct 2004	1 MB	AN-364-1.0
AN 363: FFT Co-Processor Reference Design	1.0	Oct 2004	1 MB	AN-363-1.0
AN 362: Stratix II Filtering Lab	1.0	Oct 2004	1 MB	AN-362-1.0
AN 361: Interfacing DDR & DDR2 SDRAM With Cyclone II Devices	1.3	Jun 2006	380 KB	AN-361-1.3
AN 360: Updating Simulation Models for the POS-PHY Level 4 MegaCore Function	1.1	Dec 2004	63 KB	AN-360-1.1
AN 359: POS-PHY Level 4 MegaCore Function Parameter Selection Calculator      Parameter Selection Calculator (2 MB)	2.0	Sep 2008	238 KB	AN-359-2.0
AN 358: Thermal Management for FPGAs	2.0	Dec 2009	260 KB	AN-358-2.0
AN 357: Error Detection & Recovery Using CRC in Altera FPGA Devices	1.4	Jul 2008	371 KB	AN-357-1.4
AN 355: Stratix II Device System Power Considerations	1.0	Jun 2004	274 KB	AN-355-1.0
AN 353: Reflow Soldering Guidelines for Lead-Free Packages	2.0	Feb 2009	155 KB	AN-353-2.0
AN 352: FPGA Peripheral Expansion & FPGA Co-Processing	1.0	Jul 2004	552 KB	AN352-1.0
AN 351: Simulating Nios II Embedded Processor Designs      AN 351 Software Files (6 KB)	1.2	Nov 2008	323 KB	AN-351-1.2
AN 350: Upgrading Nios Processor Systems to the Nios II Processor	1.1	Jul 2006	617 KB	AN-350-1.1
AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices	1.0	May 2004	280 KB	AN-349-1.0
AN 348: Interfacing DDR SDRAM with Cyclone Devices	1.1	Jul 2004	441 KB	AN-348-1.1
AN 347: Farrow-Based Decimating Sample Rate Converter	1.0	Mar 2004	256 KB	AN-347-1.0
AN 346: Using the Nios II Configuration Controller Reference Designs	1.2	Mar 2009	793 KB	AN-346-1.2
AN 345: Altera Design Flow for Lattice Semiconductor Users	1.1	Jan 2005	581 KB	AN-345-1.1
AN 344: ASI Demonstration	2.0	Oct 2006	145 KB	AN-344-2.0
AN 343: OpenCore Evaluation of AMPP Megafunctions	1.0	Feb 2004	294 KB	AN-343-1.0
AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices	2.0	Dec 2005	428 KB	AN-342-2.0
AN 341: Using the Design Security Feature in Stratix II and Stratix II GX Devices	2.3	Sep 2009	1 MB	AN-341-2.3
AN 340: Altera Software Licensing	2.3	Mar 2009	824 KB	AN-340-2.3
AN 339: Serial Digital Interface Demonstration for Stratix II GX Devices	3.3	May 2007	288 KB	AN-339
AN 336: Using External Series and Parallel Termination with Stratix and Stratix GX Devices	1.0	Nov 2003	1 MB	AN-336-1.0
AN 335: POS-PHY Level 4 MegaCore Function v2.1.0 Wrapper Features	1.0	Jan 2004	282 KB	AN-335-1.0
AN 334: ADI Parallel Port SDRAM Controller Reference Design	1.3	Jun 2005	753 KB	AN-334-1.3
AN 333: Developing Peripherals for SOPC Builder      Slave Peripheral Design Files (455 KB)      Streaming Slave 1C20 Design Files (1 MB)      Streaming Slave 1S10 Design Files (1 MB)      Streaming Slave 1S10ES Design Files (1 MB)      Streaming Slave 1S40 Design Files (1 MB)	1.0	Apr 2004	267 KB	AN-333-1.0
AN 332: Link-Port Reference Design	1.3	Feb 2005	1 MB	AN-332
AN 330: Connecting Altera 3.3-V PCI devices to a 5-V PCI Bus	1.0	Feb 2004	112 KB	AN-330-1.0
AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices	1.0	Mar 2004	165 KB	AN-329-1.0
AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices      ALTMEMPHY Example (604 KB)      Legacy PHY Example (330 KB)	6.0	Oct 2009	3 MB	AN-328-6.0
AN 327: Interfacing DDR SDRAM with Stratix II Devices	3.2	Sep 2008	938 KB	AN-327-3.2
AN 326: Interfacing QDRII+ & QDRII with Stratix II, Stratix II GX, Stratix, & Stratix GX Devices	5.1	May 2008	2 MB	AN-326-5.1
AN 325: Interfacing RLDRAM II with Stratix II, Stratix & Stratix GX Devices	3.1	Nov 2005	2 MB	AN-325-3.1
AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems	1.1	Nov 2007	386 KB	AN-323-1.1
AN 322: Porting the Nios GERMS Monitor to Work with Different Flash Memories	1.0	Sep 2003	139 KB	AN-322-1.0
AN 320: OpenCore Plus Evaluation of Megafunctions	1.6	Nov 2007	307 KB	AN-320-1.6
AN 317: Turbo Encoder Co-processor Reference Design	1.2	Oct 2003	183 KB	AN-317-1.2
AN 316: High-Speed Data Interface for Stratix Devices & Fujitsu MB86064 DACs	1.0	Jul 2003	402 KB	AN-316-1.0
AN 315: Guidelines for Designing High-Speed FPGA PCBs	1.1	Feb 2004	2 MB	AN-315-1.1
AN 314: Digital Predistortion Reference Design	1.0	Jul 2003	1 MB	AN-314
AN 313: Implementing Clock Switchover in Stratix & Stratix GX Devices      Clock Switchover Example Design (233 KB)	1.0	Jan 2004	273 KB	AN-313-1.0
AN 311: ASIC-to-FPGA Design Methodology and Guidelines	3.1	Apr 2009	286 KB	AN-311-3.1
AN 308: Building Embedded Processor Systems Using SOPC Builder & Excalibur Devices      AN 308: Design Files (6 MB)	1.0	Mar 2003	1 MB	AN-308-1.0
AN 307: Altera Design Flow for Xilinx Users      an307_DesignExample.zip (4 KB)	6.3	Nov 2009	2 MB	AN-307-6.3
AN 306: Implementing Multipliers in FPGA Devices	3.0	Jul 2004	733 KB	AN-306-3.0
AN 299: System Development Tools for Excalibur Devices	1.1	Jun 2003	618 KB	AN-299-1.1
AN 298: Reconfiguring Excalibur Devices Under Processor Control      AN 298: Design Files (1 MB)	1.0	Feb 2003	705 KB	AN-298-1.0
AN 294: Crosspoint Switch Matrices in MAX II & MAX 3000A Devices      16 x 16 Crosspoint Switch (6 KB)      Customized Crosspoint Switch (7 KB)	2.0	Mar 2004	205 KB	AN-294-2.0
AN 293: Using MAX 7000B Devices to Replace I/O Drivers	1.1	Nov 2005	233 KB	AN-293-1.1
AN 287: Using Excalibur DMA Controllers for Video Imaging      AN 287: Design Files (7 MB)	1.1	Feb 2003	664 KB	AN-287-1.1
AN 286: Implementing LED Drivers in MAX and MAX II Devices	2.3	Oct 2008	164 KB	AN-286-2.3
AN 284: Implementing Interrupt Service Routines in Nios Systems      Example Code (5 KB)	1.0	Jan 2003	335 KB	AN-284-1.0
AN 283: Simulating Altera Devices with IBIS Models	1.1	Nov 2003	166 KB	AN-283-1.1
AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX Devices      Example 1: Shift Register in LEs (340 KB)      Example 2: altpll_reconfig Design with the MIF (192 KB)      Example 3: altpll_reconfig Design (192 KB)	2.0	Dec 2005	511 KB	AN-282-2.0
AN 278: Excalibur Dynamic Reconfiguration with Linux Demonstration      AN 278: Design Files (17 MB)	2.0	Jun 2003	811 KB	AN-278-2.0
AN 267: Rebuilding the Excalibur Dynamic Reconfiguration with Linux Demonstration	1.0	Jun 2003	318 KB	AN-267-1.0
AN 265: Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander	2.0	Mar 2004	306 KB	AN-265-2.0
AN 263: CORDIC Reference Design	1.4	Jun 2005	323 KB	AN-263
AN 247: Stratix GX to Mercury Interoperability	1.2	Jan 2004	82 KB	AN-247-1.2
AN 245: Filtering Reference Design Lab	3.0	Dec 2004	670 KB	AN-245-3.0
AN 244: Using Run-From-Flash Mode with the Excalibur Bootloader	1.0	Sep 2002	140 KB	AN-244-1.0
AN 242: Excalibur Solutions - Simple Excalibur System      AN 242: Design Files (468 KB)	1.0	Aug 2002	245 KB	AN-242-1.0
AN 240: Simulating Excalibur Systems	1.0	Sep 2002	335 KB	AN-240-1.0
AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices	1.1	Jan 2003	177 KB	AN-236-1.1
AN 228: SPI-4.2 Interoperability with PMC-Sierra XENON Family in Stratix GX Devices	1.0	May 2003	633 KB	AN-228-1.0
AN 227: SPI-4.2 Interoperability with the Intel IXF1110 in Stratix GX Devices	1.0	May 2003	456 KB	AN-227-1.0
AN 224: High-Speed Board Layout Guidelines	1.2	Aug 2009	494 KB	AN-224-1.2
AN 223: PCI-to-DDR SDRAM Reference Design	1.0	May 2003	507 KB	AN-223-1.0
AN 213: Excalibur Remote Reconfiguration Demonstration Design      AN 213: Design Files (2 MB)	1.0	Feb 2003	2 MB	AN-213-1.0
AN 210: Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Designs	2.0	Nov 2002	143 KB	AN-210-2.0
AN 196: Excalibur Software Debugging Solutions	1.2	Aug 2002	147 KB	AN-196-1.2
AN 192: Excalibur Solutions - Embedded Stripe Performance Designs      AN 192: Design Files (346 KB)	1.2	Nov 2002	253 KB	AN-192-1.2
AN 191: Excalibur Solutions - Using the Interrupt Controller      AN 191: Design Files (370 KB)	1.3	Dec 2002	202 KB	AN-191-1.3
AN 189: Simulating Nios Embedded Processor Designs	2.1	Feb 2003	1 MB	AN-189-2.1
AN 188: Custom Instructions for the Nios Embedded Processor	1.2	Sep 2002	313 KB	AN-188-1.2
AN 187: Booting Excalibur Devices      AN 187: Design Files (574 KB)	1.2	Mar 2003	632 KB	AN-187-1.2
AN 186: Using Flexible-LVDS Circuitry in Mercury Devices	1.1	Nov 2002	264 KB	AN-186-1.1
AN 185: Thermal Management Using Heat Sinks	2.1	Mar 2002	254 KB	A-AN-185-2.1
AN 184: Simultaneous Multi-Mastering with the Avalon Bus	1.1	Apr 2002	135 KB	AN-184-1.1
AN 183: ZBT SRAM Controller Reference Design for APEX II Devices	1.0	Dec 2001	211 KB	A-AN-183-1.0
AN 181: Excalibur Solutions - Multi-Master Reference Design      AN 181: Design Files (804 KB)	2.3	Nov 2002	642 KB	AN-181-2.3
AN 180: POS-PHY Level 4-POS-PHY Level 3 Bridge Reference Design	1.02	Oct 2001	545 KB	A-AN-180-1.02
AN 179: Designing with ESBs in APEX II Devices	1.0	Mar 2002	4 MB	A-AN-179-1.0
AN 178: Estimating Nios Resource Usage & Performance	1.0	Sep 2001	224 KB	A-AN-178-1.0
AN 177: Excalibur Solutions-Using the Excalibur Stripe PLLs	1.3	Jul 2002	300 KB	A-AN-177-1.3
AN 173: Excalibur Solutions - DPRAM Reference Design      AN 173: Design Files (326 KB)	2.3	Aug 2002	208 KB	A-AN-173-2.3
AN 167: Using Flexible-LVDS I/O Pins in APEX II Devices	1.1	Aug 2002	141 KB	A-AN-167-1.1
AN 166: Using High-Speed I/O Standards in APEX II Devices	1.	May 2003	463 KB	AN-166-1.8
AN 159: Using HSDI in Source-Synchronous Mode in Mercury Devices	1.1	Dec 2002	246 KB	AN-159-1.1
AN 156: Using General-Purpose PLLs with APEX II Devices	1.5	Feb 2003	431 KB	AN-156-1.5
AN 143: Excalibur Solutions - Using the Expansion bus Interface	1.0	Oct 2002	991 KB	A-AN143-1.0
AN 142: Excalibur Solutions - Using the Embedded Stripe Bridges	2.1	Jun 2002	432 KB	A-AN142-2.1
AN 141: Excalibur Solutions - Using the SDRAM Controller	1.0	Sep 2002	926 KB	A-AN141-1.0
AN 138: LVDS Signaling Using APEX Devices I/O Pins	1.0	May 2001	229 KB	A-AN-138-01
AN 134: Using Programmable I/O Standards in Mercury Devices	2.1	Dec 2002	506 KB	AN-134-2.1
AN 132: Implementing Multiprotocol Label Switching with Altera PLDs	1.0	Jan 2001	177 KB	A-AN-132-01
AN 131: Using General Purpose PLLs in Mercury Devices	1.1	Oct 2001	616 KB	A-AN-131-1.1
AN 130: CDR in Mercury Devices	1.0	Feb 2001	225 KB	A-AN-130-01
AN 128: Implementing Voice Over Internet Protocol	1.1	Sep 2000	188 KB	A-AN-128-01.1
AN 120: Using LVDS in APEX 20KE Devices	1.5	Aug 2009	1 MB	AN-120-1.5
AN 119: Implementing High-Speed Search Applications with Altera CAM      Source code for fully associative cache (5 KB)      Source code for direct mapped cache (5 KB)	2.1	Jul 2001	2 MB	A-AN-119-2.1
AN 117: Using Selectable I/O Standards in APEX 20KE, APEX 20KC & MAX 7000B Devices	2.2	Dec 2001	1 MB	A-AN-117-2.2
AN 115: Using the ClockLock & ClockBoost PLL Features in APEX Devices	2.6	Nov 2003	557 KB	AN-115-2.6
AN 114: Designing with High-Density BGA Packages for Altera Devices	5.1	Dec 2007	574 KB	AN-114-5.1
AN 113: Plastic Package Reliability & Testing	1.0	Jun 1999	180 KB	A-AN-133-01
AN 112: Integrating Product-Term Logic in APEX 20K Devices	1.0	Apr 1999	184 KB	A-AN-112-01
AN 111: Embedded Programming Using the 8051 and Jam Byte-Code	1.2	Sep 2008	289 KB	AN-111-1.2
AN 110: Gate Counting Methodology for APEX 20K Devices	1.01	Sep 1999	169 KB	A-AN-110-01.01
AN 109: Using the HP 3070 Tester for In-System Programming	1.2	Jan 2003	123 KB	AN-109-1.2
AN 107: Using Altera Devices in Multi-Voltage Systems	2.0	Aug 2001	207 KB	A-AN-107-2.0
AN 106: Designing with 2.5-V Devices	1.01	Jul 1999	352 KB	A-AN-106-01.01
AN 102: Improving Performance in FLEX 10K Devices with Leonardo Spectrum Software	1.0	Jun 1999	450 KB	A-AN-102-01.01
AN 101: Improving Performance in FLEX 10K Devices with the Synplify Software	1.0	Oct 1998	696 KB	A-AN-101-01
AN 100: In-System Programmability Guidelines	3.0	May 1999	217 KB	AN-100-3.0
AN 95: In-System Programmability in MAX Devices	1.5	Sep 2005	123 KB	AN-095-1.5
AN 94: Understanding MAX 7000 Timing	2.0	May 1999	216 KB	A-AN-094-02
AN 92: Understanding FLEX 6000 Timing	2.0	May 1999	244 KB	A-AN-107-01
AN 91: Understanding FLEX 10K Timing	2.0	May 1999	301 KB	A-AN-091-02
AN 90: SameFrame Pin-Out Design for FineLine BGA Packages	1.01	Sep 2000	277 KB	A-AN-090-01.01
AN 83: Binary Numbering Systems	1.0	Apr 1997	174 KB	A-AN-083-01
AN 82: Highly Optimized 2-D Convolver	1.0	Feb 1997	285 KB	A-AN-082-01
AN 81: Reflow Soldering Guidelines for Surface-Mount Devices	4.0	Jun 2002	147 KB	AN-081-04
AN 80: Selecting Sockets for Altera Devices	3.0	Jan 1999	152 KB	A-AN-080-03
AN 79: Understanding FLASHlogic Timing	1.0	Jun 1996	311 KB	A-AN-079-01
AN 78: Understanding MAX 5000 & Classic Timing	3.0	May 1999	230 KB	A-AN-078-03
AN 77: Understanding MAX 9000 Timing	3.0	May 1999	239 KB	A-AN-077-03
AN 76: Understanding FLEX 8000 Timing	3.0	May 1999	207 KB	A-AN-076-03
AN 75: High-Speed Board Designs	4.0	Nov 2001	768 KB	A-AN-75-4.0
AN 74: Evaluating Power for Altera Devices	3.1	Jul 2001	512 KB	A-AN-074-03.1
AN 73: Implementing FIR Filters in FLEX Devices	1.0	Feb 1998	205 KB	A-AN-073-01.01
AN 71: Guidelines for Handling J-Lead & QFP Devices	4.0	Jan 1999	303 KB	A-AN-071-04
AN 51: Using Programmable Logic for Gate Array Designs	1.0	Jan 1996	303 KB	A-AN-051-01
AN 49: Implementing CRCCs in Altera Devices	2.1	Oct 2005	146 KB	AN-049-2.1
AN 46: ATM Packet Scheduler in FLEX 8000 Devices	1.0	Mar 1995	248 KB	A-AN-046-01
AN 45: Configuring FLASHlogic Devices	1.0	Apr 1995	159 KB	A-AN-045-01
AN 43: Designing for MAX 9000 Devices	1.0	Aug 1995	179 KB	A-AN-043-01
AN 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices	6.0	Jun 2005	360 KB	AN-039-6.0
AN 38: Configuring Multiple FLEX 8000 Devices	2.01	May 1994	442 KB	A-AN-038-2.01
AN 36: Designing with FLEX 8000 Devices	2.0	May 1994	218 KB	A-AN-036-02
AN 33: Configuring FLEX 8000 Devices	3.03	Jun 2000	401 KB	A-AN-033-3.03

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