文档资料中文版
一般器件文件
- 采用带有收发器的全系列40-nm FPGA 和ASIC 实现创新设计 (1.0版, 2009年2月, 1.25mb)
- 在40-nm工艺节点实现世界上最先进的定制逻辑器件 (1.1版, 2009年2月,855kb)
文档资料英文版
Arria II GX Device Handbook (14 MB)
Arria II GX Device Handbook Volume 1 (ver 2.0, Nov 2009, 6 MB)
Chapter 1. Arria II GX Device Family Overview (ver 2.0, Nov 2009, 256 KB) - Chapter 2. Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices (ver 1.1, Jun 2009, 278 KB)
- Chapter 3. Memory Blocks in Arria II GX Devices (ver 2.0, Nov 2009, 435 KB)
- Chapter 4. DSP Blocks in Arria II GX Devices (ver 2.0, Nov 2009, 907 KB)
- Chapter 5. Clock Networks and PLLs in Arria II GX Devices (ver 2.0, Nov 2009, 982 KB)
- Chapter 6. I/O Features in Arria II GX Devices (ver 2.0, Nov 2009, 677 KB)
- Chapter 7. External Memory Interfaces in Arria II GX Devices (ver 2.0, Nov 2009, 751 KB)
- Chapter 8. High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices (ver 2.0, Nov 2009, 915 KB)
- Chapter 9. Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices (ver 2.0, Nov 2009, 1 MB)
- Chapter 10. SEU Mitigation in Arria II GX Devices (ver 2.0, Nov 2009, 177 KB)
- Chapter 11. JTAG Boundary-Scan Testing (ver 2.0, Nov 2009, 169 KB)
- Chapter 12. Power Requirements for Arria II GX Devices (ver 1.1, Jun 2009, 76 KB)
Section I. Device Core (3 MB)
Section II. I/O Interfaces (2 MB)
Section III. System Integration (2 MB)
Arria II GX Device Handbook Volume 2 (ver 1.3, Nov 2009, 8 MB)
- Chapter 1. Arria II GX Transceiver Architecture (ver 2.1, Nov 2009, 5 MB)
- Chapter 2. Arria II GX Transceiver Clocking (ver 1.1, Nov 2009, 2 MB)
- Chapter 3. Configuring Multiple Protocols and Data Rates (ver 1.0, Feb 2009, 335 KB)
- Chapter 4. Reset Control and Power Down (ver 1.1, Mar 2009, 743 KB)
Section I. Transceiver Architecture (7 MB)
Arria II GX Device Handbook Volume 3 (ver 2.2, Feb 2010, 500 KB)
- Chapter 1. Arria II GX Device Data Sheet (ver 2.2, Feb 2010, 413 KB)
- Chapter 2. Addendum to the Arria II GX Device Handbook (ver 1.0, Jan 2010, 49 KB)
Section I. Arria II GX Device Data Sheet and Addendum (463 KB)
Related Documentation
Power and Thermal Management
- Arria II GX PowerPlay Early Power Estimator (ver 9.1 SP1, Jan 2010, 7 KB)
Arria II GX EPE user guide (600 KB)
- Device-Specific Power Delivery Network (PDN) Tool User Guide (ver 1.0, Nov 2009, 880 KB)
Power Delivery Network (PDN) Tool for Arria II GX Devices (2 MB)
Power Deliver Network (PDN) Tool for Stratix IV Devices (2 MB)
Power Delivery Network (PDN) Tool for Stratix III Devices (2 MB)
- PowerPlay Early Power Estimator User Guide (ver 1.1, Jan 2010, 600 KB)
- PowerPlay Early Power Estimator User Guide for Arria II GX FPGAs (ver 1.0, Mar 2009, 1 MB)
I/O Interfaces, Protocols and Signal Integrity
- AN 456: PCI Express High Performance Reference Design (ver 1.2, Aug 2009, 379 KB)
- Transceiver Poster (ver 1.0, Feb 2009, 191 KB)
- AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices (ver 2.1, Jan 2010, 3 MB)
- Early SSN Estimator User Guide for Altera Programmable Devices (ver 1.0, Nov 2009, 788 KB)
Arria II GX Early SSN Estimator (387 KB)
- Understanding 40-nm FPGA Solutions for SATA/SAS (ver 1.3, Mar 2009, 404 KB)
DSP
- Altera Product Catalog (ver 7.4, Mar 2010, 3 MB)
- Designing military DSP applications (ver 1.0, Apr 2009, 288 KB)
Design Guidelines
- AN 563: Arria II GX Design Guidelines (ver 1.0, Feb 2009, 752 KB)
- AN 601: Serial Digital Interface Reference Design for Arria II GX Devices (ver 1.1, Feb 2010, 582 KB)
Design Files for AN 601 (3 MB)
- Arria II GX Device Family Pin Connection Guidelines (ver 1.3, Feb 2010, 89 KB)
Development Kits
- Arria II GX FPGA Development Kit User Guide (ver 1.0, Jul 2009, 2 MB)
- Altera Product Catalog (ver 7.4, Mar 2010, 3 MB)
- Arria II GX FPGA Development Board Reference Manual (ver 1.1, Oct 2009, 2 MB)
- Broadcast design solutions from Altera (ver 1.0, Feb 2009, 156 KB)
End Applications
- Broadcast design solutions from Altera (ver 1.0, Feb 2009, 156 KB)
- Designing base transceiver station (BTS) channel cards with transceiver FPGAs and ASICs (ver 1.0, Feb 2009, 141 KB)
- Designing military DSP applications (ver 1.0, Apr 2009, 288 KB)
- Designing remote radio head applications with transceiver FPGAs (ver 1.0, Feb 2009, 164 KB)
- Enabling Ethernet-Over-NG-SONET/SDH/PDH Solutions for MSPP Linecards (ver 1.0, Apr 2009, 102 KB)
- Enabling your core-to-edge applications for net-centric warfare (ver 2.0, Jun 2009, 139 KB)
- FPGA companion chip solutions from Altera (ver 1.0, Nov 2009, 283 KB)
- GPON solutions from Altera (ver 2.0, Feb 2009, 143 KB)
- Implementing a Multirate Uncompressed Video Interface for Broadcast Applications (ver 1.0, Mar 2009, 526 KB)
- Leveraging Cost-Optimized FPGAs to Deliver OTN Mapper Solutions (ver 1.0, Oct 2009, 652 KB)
- Optical Transport Networks for 100G Implementation in FPGAs (ver 1.0, Oct 2009, 1 MB)
- Remote Radio Heads and the Evolution Towards 4G Networks (ver 1.1, Feb 2009, 718 KB)
(Radiocomp)
- Simplifying Simultaneous Multimode RRH Hardware Design (ver 1.0, Mar 2009, 1 MB)
- Video and image processing solutions for military applications (ver 2.0, Jun 2009, 278 KB)
General Device Documentation
- Innovating With a Full Spectrum of 40-nm FPGAs and ASICs With Transceivers (ver 1.3, Mar 2009, 932 KB)
- Leveraging the 40-nm Process Node to Deliver the World's Most Advanced Custom Logic Devices (ver 1.1, Feb 2009, 377 KB)
