Literature: Conference Papers

Displayed below are conference papers that have been presented at industry sponsored events by Altera^® engineers, partners, third-party vendors, customers, and various other contributors.

These papers are protected under Altera Corporation and other third party Copyrights as indicated on the copyright notice for each paper.

Title	Doc Version	Release Date	File Size	Document Part Number
Conference Paper
A Fast Algorithm to Instantly Predict FPGA SSN for Various I/O Pin Assignments (presented at DesignCon 2008)	1.0	Feb 2008	298 KB	CP-01035-1.0
A Jitter Estimation Method for Cascaded, Programmable Phase-Locked Loops (presented at DesignCon 2008)	1.0	Feb 2008	437 KB	CP-01036-1.0
A New Physical Mechanism-Based Jitter Classification Method and Its Applications (DesignCon 2009)	1.0	Feb 2009	131 KB	CP-01052-1.0
A Reset Control Apparatus for PLL Power-Up Sequence and Auto-Synchronization (presented at DesignCon 2008)	1.0	Feb 2008	54 KB	CP-01037-1.0
A Simple Data Pre-Distortion Technique for Satellite Communications (presented at GSPx)	1.0	Mar 2005	2 MB	CF-SAT031505-1.0
Accurate Calibration and Measurement of Non-Insertable Fixtures in FPGA and ASIC Device Characterization (presented at DesignCon 2006)	1.0	Feb 2006	500 KB	CP-ACMFIX-1.0
Accurate Predictions of Flip Chip BGA Warpage (presented at ECTC 2003)	1.0	Apr 2003	289 KB	CP-01017-1.0
Adaptive Edge Detection for Real-Time Video Processing using FPGAs (presented at GSPx)	1.0	Mar 2005	341 KB	CF-EDG031505-1.0
An FPGA Framework Supporting SPR and Rapid Development of SDR Applications (SDR Forum 2007 - BittWare)	1.0	Nov 2007	482 KB	CP-01034-1.0
Analysis of Crosstalk Effects on Jitter in Transcievers (presented at DesignCon 2008)	1.0	Feb 2008	223 KB	CP-01039-1.0
Analysis of FPGA Simultaneous Switching Noise in Three Domains: Time, Frequency, and Spectrum (presented at DesignCon 2006)	1.0	Feb 2006	982 KB	CP-SIMSWIT-1.0
Architecture and Methodology of a SOPC with 3.25Gbps CDR based Serdes and 1Gbps Dynamic Phase Alignment (presented at CICC 2003)	1.0	Mar 2005	165 KB	CF-031105-1.0
ASIC Prototyping in 90-nm FPGAs (Mentor Graphics User2User Conference)	2.0	Sep 2005	2 MB	CF-FPGA05-2.0
Automated Generation of Hardware Accelerators From Standard C (presented at ESC 2007)	1.0	Apr 2007	564 KB	CP-01027-1.0
Building Reliability Into Full-Array BGAs (presented at IEMT 2000)	1.0	Jul 2000	442 KB	CP-01019-1.0
Calibration Techniques for High-Bandwidth Source-Synchronous Interfaces (presented at DesignCon 2007)	1.0	Jan 2007	229 KB	CP-01024-1.0
Challenges in Implementing DDR3 Memory Interface on PCB Systems: A Methodology for Interfacing DDR3 SDRAM DIMM to an FPGA (presented at DesignCon 2008)	1.1	Feb 2008	749 KB	CP-01044-1.1
Challenges in Manufacturing Reliable Lead-Free Components (presented at JEDEC 2003)	1.0	Oct 2006	2 MB	CP-01012-1.0
Comparison of Substrate Finishes for Flip Chip Packages (presented at ECTC 2005)	1.0	Oct 2006	532 KB	CP-01013-1.0
Creating an Ethernet Messaging Application (presented at ESC 2004)	1.0	Mar 2005	1 MB	CF-EMA031105-1.0
Cyclone™: A Low-Cost, High-Performance FPGA (presented at CICC 2003)	1.0	Mar 2005	1 MB	CF-C031105-1.0
Design Guidance for the Mechanical Reliability of Low-K Flip Chip BGA Package (presented at IMAPS 2004)	1.0	Oct 2004	589 KB	CP-01018-1.0
Design Guidelines for Optimal Results in FPGAs (presented at DVCON 2003)	1.0	Mar 2005	1 MB	CF-031405-1.0
Design Methodology for Hardware Acceleration for DSP (presented at GSPx 2003)	1.0	Mar 2005	232 KB	CF-DSP031405-1.0
Design of 3.125 Gb/s Interconnect for High-bandwidth FPGAs (presented at DesignCon 2004)	1.0	Mar 2005	3 MB	CF-031505-1.0
Design Security With Waveforms (presented at SDRForum)	1.0	Nov 2005	124 KB	CP-WFRMS-1.0
Developing and Integrating FPGA Co-processors with the Tic6x Family of DSP Processors (presented at ESC 2004)	1.0	Mar 2005	1 MB	CF-031605-1.0
Digitally Assisted Adaptive Equalizer in 90 nm With Wide Range Support From 2.5 Gbps-6.5 Gbps (presented at DesignCon 2007)	1.1	Apr 2007	5 MB	CP-01026-1.1
Direct Up-Conversion using an FPGA-based Polyphase Modem (presented at GSPx)	1.0	Mar 2005	240 KB	CF-POL031505-1.0
Emerging Standards at ~10 Gbps for Wireline Communications and Associated Integrated Circuit Design and Validation (presented at CICC 2009)	1.0	Nov 2009	287 KB	CP-01057-1.0
Enabling Real-Time JPEG2000 with FPGA Architectures (presented at GSPx)	1.0	Mar 2005	2 MB	CF-JPG031505-1.0
Equalization Challenges for 6-Gbps Transceivers Addressed by PELE—A Software-Focused Solution (presented at DesignCon 2007)	1.0	Jan 2007	3 MB	CP-01025-1.0
Evaluations of Package Technologies for Power Distribution Network Decoupling by Measurement and Correlation (ECTC 2008)	1.0	May 2008	154 KB	CP-01045-1.0
Extending the Peripheral Set of DSP Processors using FPGAs (presented at GSPx)	1.0	Mar 2005	1 MB	CF-PER031505-1.0
Fail-Safe FPGA Design Features for High-Reliability Systems (ESC 2009)	1.0	Apr 2009	668 KB	CP-01053-1.0
Fail-Safe FPGA Design Features for High-Reliability Systems (MILCOM 2009)	1.0	Oct 2009	433 KB	CP-01058-1.0
Fast Time-Domain Simulation of 200+ Port S-Parameter Package Models (presented at DesignCon 2006)	1.0	Feb 2006	1 MB	CP-FTDSIMLTN-1.0
Flexural Strength of BGA Solder Joints with ENIG Substrate Finish using 4-Point Bend Test (SMTA Pan-Pacific Symposium Paper)	1.0	Mar 2005	2 MB	CF-FSB032105-1.0
FPGA Co-Processing Architectures for Video Compression (presented at GSPx)	1.0	Nov 2005	94 KB	CP-VIDEO-1.0
FPGA Co-Processing Solutions for High Performance Signal Processing Applications (presented at GSPx)	1.0	Mar 2005	318 KB	CF-COP031505-1.0
FPGA Design for Signal and Power Integrity (presented at DesignCon 2007)	1.0	Jan 2007	1 MB	CP-01023-1.0
FPGA Floating Point Datapath Compiler (FCCM 2009)	1.0	Apr 2009	236 KB	CP-01054-1.0
FPGA I/O Timing Variations Due to Simultaneous Switching Outputs (presented at DesignCon 2008)	1.0	Feb 2008	369 KB	CP-01041-1.0
FPGA Incremental Compilation—Divide and Conquer (presented at Mentor User2User 2006)	1.0	Oct 2006	181 KB	CP-01001-1.0
FPGA-Based WiMAX System Design (presented at GSPx)	1.0	Nov 2005	149 KB	CP-WIMAX-1.0
FPGAs Provide Reconfigurable DSP Solutions (presented at GSPx 2003)	1.0	Mar 2005	380 KB	CF-031705-1.0
Fracturable FPGA Logic Elements (presented at TVLSI 2006)	1.0	May 2006	317 KB	CP-01006-1.0
Functional Verification of 622-Mbps - 6.375-Gbps Transceiver IP in an FPGA (presented at DesignCon 2006)	1.0	Feb 2006	1 MB	CP-TRNSCVR-1.0
High-Performance Floating-Point Implementation Using FPGAs (MILCOM 2009)	1.0	Oct 2009	59 KB	CP-01059-1.0
How FPGAs Enable Automotive Systems (presented at GSPx)	1.0	Nov 2005	149 KB	CP-AUTO05-1.0
Implementing an FPGA-Based Broadband Modem Using Model-Based Design (presented at GSPx)	1.0	Nov 2005	222 KB	CP-BRDBND05-1.0
Implementing FFT in an FPGA Co-Processor (presented at GSPx)	1.0	Mar 2005	1 MB	CF-FFT031505-1.0
Improving FPGA Performance and Area Using an Adaptive Logic Module (presented at FPGA 2004)	1.0	Aug 2004	299 KB	CP-01004-1.0
Incorporating SSN Analysis in Constraint-Based System Design (DesignCon 2009)	1.0	Feb 2009	395 KB	CP-01050-1.0
Increasing Productivity With Altera Quartus II to I/O Designer/Dx Designer Interface (presented at Mentor User2User 2006)	1.0	Oct 2006	2 MB	CP-01002-1.0
It’s All About Timing: From Precision RTL Synthesis to Quartus II Software (presented at Mentor User2User 2007)	1.0	Mar 2007	225 KB	CP-01029-1.0
Jitter and Signal Integrity Verification for Synchronous and Asynchronous I/Os at Multiple to 10 GHz/Gbps (ITC 2008)	1.0	Oct 2008	291 KB	CP-01049-1.0
Logic Optimization Techniques for Multiplexers (presented at Mentor User2User 2004)	1.0	Oct 2006	264 KB	CP-01003-1.0
Low-Cost Solutions for Video Compression Systems (presented at GSPx)	1.0	Nov 2005	166 KB	CP-LWCST05-1.0
Low-Power Software-Defined Radio Design Using FPGAs (presented at SDRForum)	1.0	Nov 2005	144 KB	CP-LWPWTDRD05-1.0
Low-Power Software-Defined Radio Design Using FPGAs (presented at SDR Forum 2006)	1.0	Nov 2006	160 KB	CP-01009-1.0
Measurements of Pre-Emphasis on Altera Stratix GX with the BERTScope 12500A	1.0	Jun 2005	1 MB	CP-STGX05-01
Method and Apparatus of Continuous PLL Adaptation to Variable Reference Input Frequency (DesignCon 2009)	1.0	Feb 2009	108 KB	CP-01051-1.0
Military Anti-Tampering Solutions Using Programmable Logic (presented at SDR Forum 2006)	1.0	Nov 2006	145 KB	CP-01007-1.0
Mixed Signal Verification of an FPGA-Embedded DDR3 SDRAM Memory Controller Using ADMS (presented at Mentor User2User 2007)	1.0	Mar 2007	290 KB	CP-01028-1.0
Modeling and Experimental Correlation of BGA Solder Joints Under PCB Bending (presented at SMTA 2006)	1.0	Sep 2006	425 KB	CP-01011-1.0
Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A (CICC 2007)	1.0	Nov 2007	259 KB	CP-01033-1.0
Modeling FPGA Current Waveform and Spectrum and PDN Noise Estimation (presented at DesignCon 2008)	1.0	Feb 2008	887 KB	CP-01042-1.0
Multi-Clock Domain TDF ATPG Testing: An Innovative Approach (SNUG Singapore 2008 and ICED 2008)	1.0	Aug 2008	77 KB	CP-01046-1.0
Power Optimization in FPGA Designs (presented at SNUG San Jose 2006)	1.0	May 2006	124 KB	CP-PWROPT-1.0
Power Optimization Innovations in 65-nm FPGAs (presented at Mentor User2User 2007)	1.0	Mar 2007	321 KB	CP-01030-1.0
Practical Hardware Debugging: Quick Notes on How to Simulate Altera's Nios II Multiprocessory Systems Using Mentor Graphics' ModelSim (presented at Mentor User2User 2007)	1.0	Mar 2007	216 KB	CP-01031-1.0
Pre-Emphasis and Equalization Parameter Optimization With Fast, Worst-Case/Multibillion-Bit Verification (presented at DesignCon 2007)	1.0	Jan 2007	3 MB	CP-01021-1.0
Process and Temperature Variations on Electrical Paramenters of Wire-Bond BGA Packages: an Impact Analysis Using Simulation-Based DOE Methodology (presented at DesignCon 2008)	1.0	Feb 2008	90 KB	CP-01040-1.0
Process-Design Co-Optimization for FPGA (ICSICT 2008)	1.0	Oct 2008	210 KB	CP-01047-1.0
Rapid FPGA Modem Design Techniques for SDRs using Altera DSP Builder (presented at GSPx)	1.0	Mar 2005	1 MB	CF-RAP031505-1.0
Receiver Offset Cancellation in 90-nm PLD Integrated SERDES (CICC 2007)	1.0	Nov 2007	241 KB	CP-01032-1.0
Reconfigurable FPGA Coprocessors: Hardware IP for Software Engineers (presented at IP/SOC 2003)	1.0	Mar 2005	194 KB	CF-032205-1.0
Reliability of Large Organic Flip-Chip Packages for Industrial Temperature Environments (presented at ECTC 2004)	1.0	Oct 2006	645 KB	CP-01014-1.0
Reliability Study of High-Pin-Count Flip-Chip BGA (presented at ECTC 2001)	1.0	Apr 2001	317 KB	CP-01016-1.0
RSA & Public Key Cryptography in FPGAs (presented at CDC 2003)	1.0	Mar 2005	1 MB	CF-032305-1.0
Serial Protocol Compliance of an FPGA-Integrated Mixed-Signal Transceiver (presented at DesignCon 2007)	1.0	Jan 2007	569 KB	CP-01022-1.0
SOC-System Jitter Resonance and Its Impact on Common Approach to the PDN Impedence (ITC 2008)	1.0	Oct 2008	165 KB	CP-01048-1.0
Soft Multipliers For DSP Applications (presented at GSPx 2003)	1.0	Mar 2005	369 KB	CF-032405-1.0
Studies on FIR Filter Pre-Emphasis for High-Speed Backplane Data Transmission (presented at GSPx)	1.0	Mar 2005	2 MB	CF-FIR031505-1.0
Study of Fundamental Limit and Packaging Technology Solutions for 40-Gbps Transceiver Package Design (presented at DesignCon 2008)	1.0	Feb 2008	270 KB	CP-01038-1.0
Synthesizing FPGA Cores for Software-Defined Radio (presented at SDR Forum 2003)	1.0	Mar 2005	1 MB	CF-SDR031405-1.0
The Stratix II Logic and Routing Architecture (presented at FPGA 2005)	1.0	Feb 2005	176 KB	CP-01005-1.0
The Use Of Hardware Acceleration in SDR Waveforms (presented at SDRForum)	1.0	Nov 2005	116 KB	CP-ASDR05-1.0
Thermal Interface Material (TIM) Design Guidance For Flip Chip BGA Package Thermal Performance (presented at IMAPS 2004)	1.0	Oct 2004	251 KB	CP-01020-1.0
Transistor Abstraction for the Functional Verification of FPGAs (presented at DAC 2006)	1.0	Oct 2006	245 KB	CP-01010-1.0
Translating Yield Learning Into Manufacturable Designs (presented at ISTFA 2006)	1.0	Nov 2006	884 KB	CP-01015-1.0
Using ASIC Prototyping to Reduce Risks	1.0	May 2005	1 MB	CF-ASIC05-1.0
Using C-to-Hardware Acceleration in FPGAs for Waveform Baseband Processing (presented at SDR Forum 2006)	1.0	Nov 2006	314 KB	CP-01008-1.0
Using Programmable Logic for Receiver Offset and Yield Enhancement (presented at DesignCon 2008)	1.0	Feb 2008	123 KB	CP-01043-1.0
Using VFTLP Data to Design for CDM Robustness (presented at EOS-ESD 2009)	1.0	Nov 2009	450 KB	CP-01056-1.0

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