Documentation: Cyclone V Devices

SoC FPGA Documentation

Cyclone V Device Handbook (15 MB)

Cyclone V Device Handbook, Volume 1: Device Overview and Datasheet (ver 1.2, Feb 2012, 2 MB)

Chapter 1. Overview for Cyclone V Device Family (ver 1.2, Feb 2012, 725 KB)
Chapter 2. Device Datasheet for Cyclone V Devices (ver 1.2, Feb 2012, 755 KB)

Cyclone V Device Handbook, Volume 2: Device Interfaces and Integration (ver 1.2, Feb 2012, 5 MB)

Section I. Device Core for Cyclone V Devices

Chapter 1. Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices (ver 1.1, Nov 2011, 601 KB)
Chapter 2. Memory Blocks in Cyclone V Devices (ver 1.0, Oct 2011, 155 KB)
Chapter 3. Variable-Precision DSP Blocks in Cyclone V Devices (ver 1.0, Oct 2011, 305 KB)
Chapter 4. Clock Networks and PLLs in Cyclone V Devices (ver 1.1, Feb 2012, 909 KB)

Section II. I/O Interfaces for Cyclone V Devices

Chapter 5. I/O Features in Cyclone V Devices (ver 1.2, Feb 2012, 1 MB)
Chapter 6. External Memory Interfaces in Cyclone V Devices (ver 1.2, Feb 2012, 947 KB)

Section III. System Integration for Cyclone V Devices

Chapter 7. Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices (ver 1.1, Nov 2011, 177 KB)
Chapter 8. SEU Mitigation in Cyclone V Devices (ver 1.0, Oct 2011, 134 KB)
Chapter 9. JTAG Boundary-Scan Testing in Cyclone V Devices (ver 1.0, Oct 2011, 153 KB)
Chapter 10. Power Management in Cyclone V Devices (ver 1.0, Oct 2011, 133 KB)

Cyclone V Device Handbook, Volume 3: Transceivers (ver 1.0, Oct 2011, 4 MB)

Chapter 1. Transceiver Architecture in Cyclone V Devices (ver 1.0, Oct 2011, 1 MB)
Chapter 2. Transceiver Clocking in Cyclone V Devices (ver 1.0, Oct 2011, 1 MB)
Chapter 3. Transceiver Reset Control and Power Down in Cyclone V Devices (ver 1.0, Oct 2011, 352 KB)
Chapter 4. Transceiver Protocol Configurations in Cyclone V Devices (ver 1.0, Oct 2011, 748 KB)
Chapter 5. Transceiver Custom Configurations in Cyclone V Devices (ver 1.0, Oct 2011, 432 KB)

Cyclone V Device Handbook, Volume 4: Device Basics (ver 1.1, Nov 2011, 6 MB)

Chapter 1. Device Interfaces and Integration Basics for Cyclone V Devices (ver 1.1, Nov 2011, 4 MB)
Chapter 2. Transceiver Basics for Cyclone V Devices (ver 1.0, Oct 2011, 1 MB)

Related Documentation

Power and Thermal Management

Achieving Lowest System Power with Low-Power 28-nm FPGAs (ver 1.0, Mar 2012, 467 KB)
Device-Specific Power Delivery Network (PDN) Tool User Guide (ver 1.0, Nov 2009, 880 KB)
     Power Delivery Network (PDN) Tool Version 11.1 for Cyclone V, Arria V, Stratix V, Cyclone IV, and Arria II GZ Devices (3 MB)
     Power Delivery Network (PDN) Tool for Arria II GX Devices (2 MB)
     Power Deliver Network (PDN) Tool for Stratix IV Devices (2 MB)
     Power Delivery Network (PDN) Tool for Stratix III Devices (2 MB)
PowerPlay Early Power Estimator User Guide (ver 6.0, Jan 2012, 2 MB)

I/O Interfaces, Protocols and Signal Integrity

Cyclone V Hard IP for PCI Express User Guide (ver 1.0, Nov 2011, 3 MB)
AN653: Implementing the CPRI Protocol using the Deterministic Latency Transceiver PHY IP Core (ver 1.0, Jan 2012, 856 KB)
an653_Reference_Design_File (346 KB)

Device Configuration and Remote System Upgrades

Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide (ver 1.1, Feb 2012, 2 MB)

Design Guidelines

Tips and Techniques for 28-nm Design Optimization (ver 1.0, Nov 2011, 704 KB)

PCB Layout and Packaging

AN659: Thermal Management and Mechanical Handling for Lidless Flip Chip Ball-Grid Array (ver 1.0, Mar 2012, 980 KB)
(This application note provides guidance on thermal management and mechanical handling of lidless flip chip ball-grid array (FCBGA) for Altera devices. )

End Applications

A Validated Methodology for Designing Safe Industrial Systems on a Chip (ver 1.0, Sep 2011, 371 KB)
Broadcast video and image processing (ver 2.1, Mar 2012, 411 KB)
Displays (ver 2.0, Mar 2012, 257 KB)

General Device Documentation

Achieving Lowest System Power with Low-Power 28-nm FPGAs (ver 1.0, Mar 2012, 467 KB)
Altera's User-Customizable ARM-Based SoC FPGAs (ver 1.0, Oct 2011, 3 MB)
Cyclone V FPGAs (ver 1.0, Mar 2012, 290 KB)
Industrial Motor Drive on a Single FPGA (ver 2.0, Mar 2012, 370 KB)
Jump-Start Software Development with the SoC FPGA Virtual Target (ver 1.0, Oct 2011, 370 KB)
Reducing Total System Cost with Low-Power 28-nm FPGAs (ver 1.1, Apr 2012, 517 KB)

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