HardCopy III Device Handbook, Volumes 1, 2, and 3 (4 MB)
HardCopy III Device Handbook, Volume 1 (ver 3.2, Jan 2010, 2 MB)
Chapter 1. HardCopy III Device Family Overview (ver 3.1, Jul 2009, 235 KB) - Chapter 2. Logic Array Block and Adaptive Logic Module Implementation in HardCopy III Devices (ver 2.0, Dec 2008, 82 KB)
- Chapter 3. DSP Block Implementation in HardCopy III Devices (ver 2.0, Dec 2008, 119 KB)
- Chapter 4. TriMatrix Embedded Memory Blocks in HardCopy III Devices (ver 3.0, Jun 2009, 84 KB)
- Chapter 5. Clock Networks and PLLs in HardCopy III Devices (ver 3.0, Jun 2009, 127 KB)
- Chapter 6. HardCopy III Device I/O Features (ver 3.0, Jun 2009, 154 KB)
- Chapter 7. External Memory Interfaces in HardCopy III Devices (ver 3.0, Jun 2009, 762 KB)
- Chapter 8. High-Speed Differential I/O Interfaces and DPA in HardCopy III Devices (ver 3.1, Jan 2010, 635 KB)
- Chapter 9. Hot Socketing and Power-On Reset in HardCopy III Devices (ver 2.0, Dec 2008, 221 KB)
- Chapter 10. IEEE 1149.1 (JTAG) Boundary Scan Testing in HardCopy III Devices (ver 3.0, Feb 2010, 103 KB)
- Chapter 11. Power Supply and Temperature Sensing Diode in HardCopy III Devices (ver 3.1, Jan 2010, 180 KB)
- Chapter 12. HardCopy III Device and Packaging Information (ver 3.0, Jun 2009, 53 KB)
Section I. Device Core (480 KB)
Section II. I/O Interfaces (1 MB)
Section III. Hot Socketing and Testing (341 KB)
Section IV. Power and Thermal Management (352 KB)
Section V. Packaging Information (162 KB)
HardCopy III Device Handbook, Volume 2 (ver 3.1, Jan 2010, 2 MB)
- Chapter 1. HardCopy III Design Flow Using the Quartus II Software (ver 3.1, Jan 2010, 1 MB)
- Chapter 2. HardCopy Design Center Implementation Process (ver 2.0, Dec 2008, 158 KB)
- Chapter 3. Mapping Stratix III Device Resources to HardCopy III Devices (ver 3.1, Jan 2010, 478 KB)
- Chapter 4. Matching Stratix III Power and Configuration Requirements with HardCopy III Devices (ver 3.0, Jun 2009, 447 KB)
Section I. HardCopy III Design Flow and Prototyping with Stratix III Devices (2 MB)
HardCopy III Device Handbook, Volume 3 (ver 3.0, Jun 2009, 397 KB)
- Chapter 1. DC and Switching Characteristics of HardCopy III Devices (ver 3.0, Jun 2009, 317 KB)
Section I. HardCopy III Device Datasheet (324 KB)
Related Documentation
External Memory Interfaces
- AN 550: Using the DLL Phase Offset Feature in Stratix FPGAs and HardCopy ASICs (ver 2.0, Mar 2010, 547 KB)
altmemphy_ext_dll.zip (48 KB)
altmemphy_int_dll.zip (47 KB)
static_dll.zip (18 KB)
- External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide (ver 7.3, Jan 2010, 3 MB)
Power and Thermal Management
- PowerPlay Early Power Estimator User Guide (ver 1.1, Jan 2010, 600 KB)
- Stratix III, Stratix IV, HardCopy III and HardCopy IV PowerPlay Early Power Estimator (ver 9.1 SP1, Jan 2010, 7 KB)
PowerPlay Early Power Estimator User Guide For Stratix III and Stratix IV FPGAs (600 KB)
I/O Interfaces, Protocols and Signal Integrity
- AN 477: Designing RGMII Interface with FPGA and HardCopy Devices (ver 2.0, Jan 2010, 519 KB)
- Input Signal Edge Rate Guidance (ver 1.0, Jun 2005, 63 KB)
DSP
- Altera Product Catalog (ver 7.4, Mar 2010, 3 MB)
Design Guidelines
- AN 311: ASIC-to-FPGA Design Methodology and Guidelines (ver 3.1, Apr 2009, 286 KB)
- AN 477: Designing RGMII Interface with FPGA and HardCopy Devices (ver 2.0, Jan 2010, 519 KB)
Development Kits
- Altera Product Catalog (ver 7.4, Mar 2010, 3 MB)
End Applications
- Altera Addresses the SWaP Challenges (ver 1.0, Sep 2007, 149 KB)
- Altera Enhanced COTS PLD Initiative (ver 1.1, Jul 2008, 122 KB)
- Altera FPGAs for radar and advanced sensors (ver 1.0, Oct 2007, 219 KB)
- Broadband access solutions from Altera (ver 1.0, Sep 2007, 263 KB)
- HardCopy ASICs (ver 1.1, Jul 2008, 277 KB)
General Device Documentation
- Altera Addresses the SWaP Challenges (ver 1.0, Sep 2007, 149 KB)
- Altera Enhanced COTS PLD Initiative (ver 1.1, Jul 2008, 122 KB)
- Altera FPGAs for radar and advanced sensors (ver 1.0, Oct 2007, 219 KB)
- Broadband access solutions from Altera (ver 1.0, Sep 2007, 263 KB)
- Generating Functionally Equivalent FPGAs and ASICs With a Single Set of RTL and Synthesis/Timing Constraints (ver 1.2, Feb 2009, 459 KB)
- HardCopy ASICs (ver 1.1, Jul 2008, 277 KB)
