资料：Nios II 处理器

这些手册是Nios^® II处理器的主要文档。

Nios II处理器参考手册回答了“什么是Nios II处理器?”这一问题，是Nios II处理器体系结构的主要参考资料。
Nios II软件开发人员手册回答了“我怎样编写Nios II处理器程序?”这一问题，是Nios II处理器编程的主要参考资料。
Quartus^® II开发软件手册，卷5：嵌入式外设介绍了Altera提供的外设，这些外设可以和Nios II处理器无缝工作，包含在Quartus II软件中。

其他相关文档，例如教程和用户指南等，涵盖了手册中未涉及的某些主题。

点击下载嵌入文档

文件简要介绍了Nios II处理器、Nios II C语言至硬件(C2H)加速编译器、SOPC Builder和嵌入式外设文档。文件解压缩后，请参考documentation.htm文件，它列出了所包含的文档。

其他文档

Nios II设计大赛论文
Nios II硬件开发
软件开发
C语言至硬件(C2H)加速编译器
开发工具、套件和电路板
SOPC Builder系统开发
使用宏功能
其他相关文档

下载最新的中文版 Nios II 小册子

Nios II Processor Reference Handbook (ver 9.0, Mar 2009, 2 MB)

Section I. Nios II Processor Design (1 MB)

Chapter 1. Introduction (ver 9.0.0, Mar 2009, 156 KB)
Chapter 2. Processor Architecture (ver 9.0.0, Mar 2009, 275 KB)
Chapter 3. Programming Model (ver 9.0.0, Mar 2009, 430 KB)
Chapter 4. Instantiating the Nios II Processor in SOPC Builder (ver 9.0.0, Mar 2009, 372 KB)

Section II. Nios II Processor Implementation and Reference (698 KB)

Chapter 5. Nios II Core Implementation Details (ver 9.0.0, Mar 2009, 212 KB)
Chapter 6. Nios II Processor Revision History (ver 9.0.0, Mar 2009, 94 KB)
Chapter 7. Application Binary Interface (ver 9.0.0, Mar 2009, 135 KB)
Chapter 8. Instruction Set Reference (ver 9.0.0, Mar 2009, 404 KB)

Nios II Software Developer's Handbook (ver 9.0, Mar 2009, 3 MB)

Porting Nios II IDE Projects to the Software Build Tools (ver 9.0.0, Mar 2009, 95 KB)

Section I. Nios II Software Development (856 KB)

Chapter 1. Overview (ver 9.0.0, Mar 2009, 222 KB)
Chapter 2. Nios II Integrated Development Environment (ver 9.0.0, Mar 2009, 165 KB)
Chapter 3. Introduction to the Nios II Software Build Tools (ver 9.0.0, Mar 2009, 150 KB)
Chapter 4. Using the Nios II Software Build Tools (ver 9.0.0, Mar 2009, 441 KB)

Section II. Hardware Abstraction Layer (872 KB)

Chapter 5. Overview of the Hardware Abstraction Layer (ver 9.0.0, Mar 2009, 127 KB)
Chapter 6. Developing Programs Using the Hardware Abstraction Layer (ver 9.0.0, Mar 2009, 507 KB)
Chapter 7. Developing Device Drivers for the Hardware Abstraction Layer (ver 9.0.0, Mar 2009, 384 KB)

Section III. Advanced Programming Topics (641 KB)

Chapter 8. Exception Handling (ver 9.0.0, Mar 2009, 270 KB)
Chapter 9. Cache and Tightly-Coupled Memory (ver 9.0.0, Mar 2009, 128 KB)
Chapter 10. MicroC/OS-II Real Time Operating System (ver 9.0.0, Mar 2009, 182 KB)
Chapter 11. Ethernet and the NicheStack TCP/IP Stack - Nios II Edition (ver 9.0.0, Mar 2009, 169 KB)
Chapter 12. Read-Only Zip File System (ver 9.0.0, Mar 2009, 83 KB)
Chapter 13. Publishing Component Information to Embedded Software (ver 9.0.0, Mar 2009, 133 KB)

Section IV. Reference Material (1 MB)

Chapter 14. HAL API Reference (ver 9.0.0, Mar 2009, 566 KB)
Chapter 15. Nios II Software Build Tools Reference (ver 9.0.0, Mar 2009, 709 KB)

Volume 5: Embedded Peripherals (ver 9.0, Mar 2009, 4 MB)

Section I. Off-Chip Interface Peripherals (2 MB)

Chapter 1. SDRAM Controller Core (ver 9.0.0, Mar 2009, 253 KB)
Chapter 2. CompactFlash Core (ver 9.0.0, Mar 2009, 115 KB)
Chapter 3. Common Flash Interface Controller Core (ver 9.0.0, Mar 2009, 107 KB)
Chapter 4. EPCS Device Controller Core (ver 9.0.0, Mar 2009, 115 KB)
Chapter 5. JTAG UART Core (ver 9.0.0, Mar 2009, 214 KB)
Chapter 6. UART Core (ver 9.0.0, Mar 2009, 243 KB)
Chapter 7. SPI Core (ver 9.0.0, Mar 2009, 202 KB)
Chapter 8. Optrex 16207 LCD Controller Core (ver 9.0.0, Mar 2009, 97 KB)
Chapter 9. PIO Core (ver 9.0.0, Mar 2009, 139 KB)
Chapter 10. Avalon-ST JTAG Interface Core (ver 9.0.0, Mar 2009, 139 KB)
Chapter 11. Avalon-ST Serial Peripheral Interface Core (ver 9.0.0, Mar 2009, 196 KB)
Chapter 12. SPI Slave/JTAG to Avalon Master Bridge Cores (ver 9.0.0, Mar 2009, 211 KB)
Chapter 13. PCI Lite Core (ver 9.0.0, Mar 2009, 345 KB)

Section II. On-Chip Storage Peripherals (2 MB)

Chapter 14. Avalon-ST Single Clock and Dual Clock FIFO Cores (ver 9.0.0, Mar 2009, 193 KB)
Chapter 15. On-Chip FIFO Memory Core (ver 9.0.0, Mar 2009, 228 KB)
Chapter 16. Avalon-ST Multi-Channel Shared Memory FIFO Core (ver 9.0.0, Mar 2009, 200 KB)

Section III. Transport and Communication (1 MB)

Chapter 17. Avalon Streaming Channel Multiplexer and Demultiplexer Cores (ver 9.0.0, Mar 2009, 129 KB)
Chapter 18. Avalon-ST Bytes to Packets and Packets to Bytes Converter Cores (ver 9.0.0, Mar 2009, 165 KB)
Chapter 19. Avalon Packets to Transactions Converter Core (ver 9.0.0, Mar 2009, 132 KB)
Chapter 20. Avalon-ST Round Robin Scheduler Core (ver 9.0.0, Mar 2009, 132 KB)

Section IV. Peripherals (2 MB)

Chapter 21. Scatter-Gather DMA Controller Core (ver 9.0.0, Mar 2009, 283 KB)
Chapter 22. DMA Controller Core (ver 9.0.0, Mar 2009, 190 KB)
Chapter 23. Video Sync Generator and Pixel Converter Cores (ver 9.0.0, Mar 2009, 144 KB)
Chapter 24. Interval Timer Core (ver 9.0.0, Mar 2009, 191 KB)
Chapter 25. System ID Core (ver 9.0.0, Mar 2009, 85 KB)
Chapter 26. Mutex Core (ver 9.0.0, Mar 2009, 110 KB)
Chapter 27. Mailbox Core (ver 9.0.0, Mar 2009, 116 KB)

Section V. Test and Debug Peripherals (1 MB)

Chapter 28. Cyclone III Remote Update Controller Core (ver 9.0.0, Mar 2009, 138 KB)
Chapter 29. Performance Counter Core (ver 9.0.0, Mar 2009, 170 KB)
Chapter 30. Avalon Streaming Test Pattern Generator and Checker Cores (ver 9.0.0, Mar 2009, 265 KB)

Section VI. Clock Control Peripherals (1 MB)

Chapter 31. PLL Core (ver 9.0.0, Mar 2009, 147 KB)

Embedded Design Handbook (ver 2.3, Apr 2009, 2 MB)

Section I. Introduction (293 KB)

Chapter 1. First-Time Designer's Guide (ver 2.1, Jan 2009, 293 KB)

Section II. Nios II Software Development (1 MB)

Chapter 2. Developing Nios II Software (ver 1.1, Jun 2008, 478 KB)
Chapter 3. Debugging Nios II Designs (ver 1.2, Apr 2009, 436 KB)
Chapter 4. Nios II Command-Line Tools (ver 2.1, Apr 2009, 152 KB)

Chapter 5. Optimizing Nios II C2H Compiler Results (ver 1.1, Jun 2008, 468 KB)

edh_c2h_optimization_design_files.zip

Section III. System Level Design (1 MB)

Chapter 6. Avalon Memory-Mapped Design Optimizations (ver 1.1, Jun 2008, 332 KB)
Chapter 7. Memory System Design (ver 1.1, Jun 2008, 198 KB)
Chapter 8. Hardware Acceleration and Coprocessing (ver 1.1, Jun 2008, 163 KB)
Chapter 9. Verification and Board Bring-Up (ver 1.2, Nov 2008, 240 KB)
Chapter 10. Interfacing an External Processor to an Altera FPGA (ver 1.0, Feb 2009, 549 KB)