Altera Home Page
文档资料 许可
在线购买 下载

  主页   |   产品   |   支持   |   最终市场   |   技术中心   |   教育与活动   |   公司介绍   |   在线购买  
  器件   |   设计软件   |   IP   |   设计服务   |   开发套件及配件   |   资料  

 CPLD
      MAX II
      MAX 3000A
      MAX 7000
  
 FPGA
      Cyclone III
      Cyclone II
      Cyclone
      Stratix III
      Stratix II
      Stratix
      Stratix II GX
      Stratix GX
      Arria GX
  
 结构化ASIC
      HardCopy
  
 按最终市场
   最终市场
  
 配置
      配置器件
  
 成熟
      成熟器件
  
 设计软件
   Quartus II
      系统级软件
      MAX+PLUS II
  
 IP/嵌入式处理器
   IP Megafunction
      Nios II 处理器
      Nios 处理器
      SOPC Builder
  
 按技术
   技术
  
 按类型
      应用简介
      应用文档
      会议文献
      数据手册
      器件管脚列表
      勘误表
      功能说明
      手册
      技术摘要
      用户指南
      白皮书
  
 一般文档资料
      年度报告
      小册子
      用户通告
      设计竞赛论文
      Altera术语集
      News & Views 新闻通讯
      订购信息
      宣传推广
      可靠性报告
      美国证管会文档
      选型指南
      Sparkle Sheet
  
 订阅电邮新闻/电子通讯
      立即订阅
      管理您的订单
      查看电子通讯存档
      News & Views Ezine
  
 文档资料更新
      立即订阅
      管理您的订单
      查看最近更新
      FAQ
  
 RSS/XML News Feeds
      立即订阅
  

News & Views

Top Story First Quarter 2006
Ensuring Serial Protocol Signal Integrity with FPGAs & Embedded Transceivers
Today's high-end field programmable gate arrays (FPGAs) with embedded transceivers support a variety of widely accepted serial protocol standards, including Gigabit Ethernet, PCI Express...

Full Story

Customer Applications Technology News
FPGAs & Structured ASICs: New Solutions for Changing Market Dynamics
Learn how to verify a design using state-of-the-art 90-nm FPGAs
Optimize System Flexibility by Integrating Custom Microprocessors into FPGAs
Overcome the inflexibility of COTS processors
Altera Programmable Solutions Accelerate Blaupunkt's Automotive Navigation Product Development
Read how Cyclone FPGAs & Nios II processors accelerate Blaupunkt's time-to-market
Multi-Processor Solutions with FPGAs
Discover the power of FPGA-based embedded systems featuring multiple processors
Tektronix, Altera & FS2 Collaborate on Real-Time Logic Debug Solution for Altera FPGAs
Find out how to increase your productivity and reduce debugging time
DE2 Development & Education Board
Use the DE2 development board to educate students on digital logic
  Partner Showcase
Synplify Pro

Bringing the FPGA on Board (Altium)

When FPGA I/O Design Becomes a Necessity (Mentor Graphics)

Best Practices: Image Processing Design and Verification (Vanteon)


Design Tips
Condensing Avalon PIOs to Achieve Timing

Enabling Clock Latency

Report Combined Fast/Slow Timing

Speed Optimization Technique for Clock Domains

.

  请填写反馈意见