For a general introduction to features and design flow in the Quartus II software, see the Introduction to Quartus II Manual.
Quartus II Handbook v9.0 (Complete Five-Volume Set) (37 MB)
Volume 1: Design and Synthesis (ver 9.0, Mar 2009, 9 MB)
Chapter 1. Design Planning with the Quartus II Software (ver 9.0.0, Mar 2009, 235 KB) - Chapter 2. Quartus II Incremental Compilation for Hierarchical and Team-Based Design (ver 9.0.0, Mar 2009, 839 KB)
- Chapter 3. Quartus II Design Flow for MAX+PLUS II Users (ver 9.0.0, Mar 2009, 1 MB)
- Chapter 4. Quartus II Support for HardCopy Series Devices (ver 9.0.0, Mar 2009, 1 MB)
- Chapter 5. Design Recommendations for Altera Devices and the Quartus II Design Assistant (ver 9.0.0, Mar 2009, 658 KB)
- Chapter 6. Recommended HDL Coding Styles (ver 9.0.0, Mar 2009, 810 KB)
- Chapter 7. Managing Metastability with the Quartus II Software (ver 9.0.0, Mar 2009, 233 KB)
- Chapter 8. Best Practices for Incremental Compilation Partitions and Floorplan Assignments (ver 9.0.0, Mar 2009, 696 KB)
- Chapter 9. Quartus II Integrated Synthesis (ver 9.0.0, Mar 2009, 906 KB)
- Chapter 10. Synopsys Synplify Support (ver 9.0.0, Mar 2009, 552 KB)
- Chapter 11. Mentor Graphics Precision Synthesis Support (ver 9.0.0, Mar 2009, 543 KB)
- Chapter 12. Mentor Graphics LeonardoSpectrum Support (ver 9.0.0, Mar 2009, 306 KB)
- Chapter 13. Analyzing Designs with Quartus II Netlist Viewers (ver 9.0.0, Mar 2009, 1 MB)
Section I. Design Flows (5 MB)
Section II. Design Guidelines (3 MB)
Section III. Synthesis (4 MB)
Volume 2: Design Implementation and Optimization (ver 9.0, Mar 2009, 11 MB)
- Chapter 1. Assignment Editor (ver 9.0.0, Mar 2009, 242 KB)
- Chapter 2. Command-Line Scripting (ver 9.0.0, Mar 2009, 402 KB)
- Chapter 3. Tcl Scripting (ver 9.0.0, Mar 2009, 2 MB)
- Chapter 4. Managing Quartus II Projects (ver 9.0.0, Mar 2009, 909 KB)
- Chapter 5. I/O Management (ver 9.0.0, Mar 2009, 2 MB)
- Chapter 6. Simultaneous Switching Noise (SSN) Analysis and Optimizations (ver 9.0.0, Mar 2009, 567 KB)
- Chapter 7. Signal Integrity with Third-Party Tools (ver 9.0.0, Mar 2009, 505 KB)
- Chapter 8. Mentor Graphics PCB Design Tools Support (ver 9.0.0, Mar 2009, 572 KB)
- Chapter 9. Cadence PCB Design Tools Support (ver 9.0.0, Mar 2009, 513 KB)
- Chapter 10. Area and Timing Optimization (ver 9.0.0, Mar 2009, 1 MB)
- Chapter 11. Power Optimization (ver 9.0.0, Mar 2009, 684 KB)
- Chapter 12. Analyzing and Optimizing the Design Floorplan (ver 9.0.0, Mar 2009, 1 MB)
- Chapter 13. Netlist Optimizations and Physical Synthesis (ver 9.0.0, Mar 2009, 266 KB)
- Chapter 14. Design Space Explorer (ver 9.0.0, Mar 2009, 212 KB)
- Chapter 15. Engineering Change Management with the Chip Planner (ver 9.0.0, Mar 2009, 629 KB)
Section I. Scripting and Constraint Entry (5 MB)
Section II. I/O and PCB Tools (5 MB)
Section III. Area, Timing and Power Optimization (4 MB)
Section IV. Engineering Change Management (2 MB)
Volume 3: Verification (ver 9.0, Mar 2009, 11 MB)
- Chapter 1. Quartus II Simulator (ver 9.0.0, Mar 2009, 418 KB)
- Chapter 2. Mentor Graphics ModelSim Support (ver 9.0.0, Mar 2009, 1,006 KB)
- Chapter 3. Synopsys VCS and VCS-MX Support (ver 9.0.0, Mar 2009, 508 KB)
- Chapter 4. Cadence NC-Sim Support (ver 9.0.0, Mar 2009, 772 KB)
- Chapter 5. Aldec Active-HDL Support (ver 9.0.0, Mar 2009, 736 KB)
- Chapter 6. Simulating Altera IP in Third-Party Simulation Tools (ver 9.0.0, Mar 2009, 207 KB)
- Chapter 7. Quartus II TimeQuest Timing Analyzer (ver 9.0.0, Mar 2009, 1 MB)
- Chapter 8. Best Practices for the Quartus II TimeQuest Timing Analyzer (ver 9.0.0, Mar 2009, 189 KB)
- Chapter 9. Switching to the Quartus II TimeQuest Timing Analyzer (ver 9.0.0, Mar 2009, 623 KB)
- Chapter 10. Quartus II Classic Timing Analyzer (ver 9.0.0, Mar 2009, 570 KB)
- Chapter 11. Synopsys PrimeTime Support (ver 9.0.0, Mar 2009, 403 KB)
- Chapter 12. PowerPlay Power Analysis (ver 9.0.0, Mar 2009, 533 KB)
- Chapter 13. Quick Design Debugging Using SignalProbe (ver 9.0.0, Mar 2009, 388 KB)
- Chapter 14. Design Debugging Using the SignalTap II Embedded Logic Analyzer (ver 9.0.0, Mar 2009, 2 MB)
- Chapter 15. In-System Debugging Using External Logic Analyzers (ver 9.0.0, Mar 2009, 276 KB)
- Chapter 16. In-System Updating of Memory and Constants (ver 9.0.0, Mar 2009, 309 KB)
- Chapter 17. Design Debugging Using In-System Sources and Probes (ver 9.0.0, Mar 2009, 340 KB)
- Chapter 18. Cadence Encounter Conformal Support (ver 9.0.0, Mar 2009, 463 KB)
- Chapter 19. Quartus II Programmer (ver 9.0.0, Mar 2009, 886 KB)
Section I. Simulation (4 MB)
Section II. Timing Analysis (4 MB)
Section III. Power Estimation and Analysis (3 MB)
Section IV. In-System Design Debugging (5 MB)
Section V. Formal Verification (3 MB)
Section VI. Device Programming (3 MB)
Volume 4: SOPC Builder (ver 9.0, Mar 2009, 2 MB)
- Chapter 1. Introduction to SOPC Builder (ver 9.0.0, Mar 2009, 176 KB)
- Chapter 2. System Interconnect Fabric for Memory-Mapped Interfaces (ver 9.0.0, Mar 2009, 289 KB)
- Chapter 3. System Interconnect Fabric for Streaming Interfaces (ver 9.0.0, Mar 2009, 110 KB)
- Chapter 4. SOPC Builder Components (ver 9.0.0, Mar 2009, 186 KB)
- Chapter 5. Using SOPC Builder with the Quartus II Software (ver 9.0.0, Mar 2009, 155 KB)
- Chapter 6. Component Editor (ver 9.0.0, Mar 2009, 155 KB)
- Chapter 7. Component Interface Tcl Reference (ver 9.0.0, Mar 2009, 372 KB)
- Chapter 8. Archiving SOPC Builder Projects (ver 9.0.0, Mar 2009, 94 KB)
- Chapter 9. SOPC Builder Memory Subsystem Development Walkthrough (ver 9.0.0, Mar 2009, 412 KB)
- Chapter 10. SOPC Builder Component Development Walkthrough (ver 9.0.0, Jul 2009, 192 KB)
- Chapter 11. Avalon Memory-Mapped Bridges (ver 9.0.0, Mar 2009, 477 KB)
- Chapter 12. Avalon Streaming Interconnect Components (ver 9.0.0, Mar 2009, 190 KB)
Section I. SOPC Builder Features (1 MB)
Section II. Building Systems with SOPC Builder (1 MB)
Section III. Interconnect Components (1 MB)
Volume 5: Embedded Peripherals (ver 9.0, Mar 2009, 4 MB)
- Chapter 1. SDRAM Controller Core (ver 9.0.0, Mar 2009, 253 KB)
- Chapter 2. CompactFlash Core (ver 9.0.0, Mar 2009, 115 KB)
- Chapter 3. Common Flash Interface Controller Core (ver 9.0.0, Mar 2009, 107 KB)
- Chapter 4. EPCS Device Controller Core (ver 9.0.0, Mar 2009, 115 KB)
- Chapter 5. JTAG UART Core (ver 9.0.0, Mar 2009, 214 KB)
- Chapter 6. UART Core (ver 9.0.0, Mar 2009, 243 KB)
- Chapter 7. SPI Core (ver 9.0.0, Mar 2009, 202 KB)
- Chapter 8. Optrex 16207 LCD Controller Core (ver 9.0.0, Mar 2009, 97 KB)
- Chapter 9. PIO Core (ver 9.0.0, Mar 2009, 139 KB)
- Chapter 10. Avalon-ST JTAG Interface Core (ver 9.0.0, Mar 2009, 139 KB)
- Chapter 11. Avalon-ST Serial Peripheral Interface Core (ver 9.0.0, Mar 2009, 196 KB)
- Chapter 12. SPI Slave/JTAG to Avalon Master Bridge Cores (ver 9.0.0, Mar 2009, 211 KB)
- Chapter 13. PCI Lite Core (ver 9.0.0, Mar 2009, 345 KB)
- Chapter 14. Avalon-ST Single Clock and Dual Clock FIFO Cores (ver 9.0.0, Mar 2009, 193 KB)
- Chapter 15. On-Chip FIFO Memory Core (ver 9.0.0, Mar 2009, 228 KB)
- Chapter 16. Avalon-ST Multi-Channel Shared Memory FIFO Core (ver 9.0.0, Mar 2009, 200 KB)
- Chapter 17. Avalon Streaming Channel Multiplexer and Demultiplexer Cores (ver 9.0.0, Mar 2009, 129 KB)
- Chapter 18. Avalon-ST Bytes to Packets and Packets to Bytes Converter Cores (ver 9.0.0, Mar 2009, 165 KB)
- Chapter 19. Avalon Packets to Transactions Converter Core (ver 9.0.0, Mar 2009, 132 KB)
- Chapter 20. Avalon-ST Round Robin Scheduler Core (ver 9.0.0, Mar 2009, 132 KB)
- Chapter 21. Scatter-Gather DMA Controller Core (ver 9.0.0, Mar 2009, 283 KB)
- Chapter 22. DMA Controller Core (ver 9.0.0, Mar 2009, 190 KB)
- Chapter 23. Video Sync Generator and Pixel Converter Cores (ver 9.0.0, Mar 2009, 144 KB)
- Chapter 24. Interval Timer Core (ver 9.0.0, Mar 2009, 191 KB)
- Chapter 25. System ID Core (ver 9.0.0, Mar 2009, 85 KB)
- Chapter 26. Mutex Core (ver 9.0.0, Mar 2009, 110 KB)
- Chapter 27. Mailbox Core (ver 9.0.0, Mar 2009, 116 KB)
- Chapter 28. Cyclone III Remote Update Controller Core (ver 9.0.0, Mar 2009, 138 KB)
- Chapter 29. Performance Counter Core (ver 9.0.0, Mar 2009, 170 KB)
- Chapter 30. Avalon Streaming Test Pattern Generator and Checker Cores (ver 9.0.0, Mar 2009, 265 KB)
- Chapter 31. PLL Core (ver 9.0.0, Mar 2009, 147 KB)
Section I. Off-Chip Interface Peripherals (2 MB)
Section II. On-Chip Storage Peripherals (2 MB)
Section III. Transport and Communication (1 MB)
Section IV. Peripherals (2 MB)
Section V. Test and Debug Peripherals (1 MB)
Section VI. Clock Control Peripherals (1 MB)
Related Documentation
Release Notes
- Quartus II Software version 9.0 SP 1 Release Notes (ver 1.0, May 2009, 303 KB)
- Quartus II Software version 9.0 SP 2 Device Support Release Notes (ver 1.0, May 2009, 100 KB)
Getting Started
- Megafunction Overview User Guide (ver 1.0, Feb 2009, 329 KB)
- Introduction to the Quartus II Software (ver 1.0, Mar 2009, 8 MB)
- Quartus II Quick Start Guide (ver 7.2, Oct 2007, 537 KB)
Installation and Licensing
- AN 340: Altera Software Licensing (ver 2.3, Mar 2009, 824 KB)
- Quartus II Installation & Licensing for Windows and Linux Workstations (ver 9.0, Mar 2009, 2 MB)
QSF Settings, SDC, and Tcl Scripting Reference Manuals
- Quartus II Settings File Reference Manual (ver 6.0, Mar 2009, 5 MB)
- Quartus II Scripting Reference Manual (ver 9.0, Mar 2009, 3 MB)
- SDC and TimeQuest API Reference Manual (ver 4.0, Mar 2009, 709 KB)
Design Guidelines and Applications
- AN 567: Quartus II Design Separation Flow (ver 1.0, Jun 2009, 3 MB)
- AN 519: Stratix IV Design Guidelines (ver 1.1, May 2009, 493 KB)
- AN 370: Using the Serial FlashLoader With the Quartus II Software (ver 3.1, Apr 2009, 1 MB)
- Quartus II TimeQuest Timing Analyzer Cookbook (ver 1.0, Aug 2008, 482 KB)
- AN 481: Applying Multicycle Exceptions in the TimeQuest Timing Analyzer (ver 1.0, Jul 2008, 2 MB)
- AN 433: Constraining and Analyzing Source-Synchronous Interfaces (ver 2.0, Dec 2007, 1 MB)
- Understanding Metastability in FPGAs (ver 1.2, Jul 2009, 584 KB)
- AN 438: Constraining and Analyzing Timing for External Memory Interfaces in Stratix IV, Stratix III, Arria II GX, and Cyclone III Devices (ver 4.1, May 2009, 976 KB)
SIII_phase_shift (5 KB)
- AN 563: Arria II GX Design Guidelines (ver 1.0, Feb 2009, 752 KB)
- AN 466: Cyclone III Design Guidelines (ver 1.2, Nov 2008, 1 MB)
- Advanced Synthesis Cookbook: A Design Guide for Stratix II, Stratix III, and Stratix IV Devices (ver 4.0, May 2008, 968 KB)
Advanced Synthesis Cookbook Design Files (3 MB)
- AN 469: Stratix III Design Guidelines (ver 1.1, May 2008, 628 KB)
- AN 474: Implementing Stratix III Programmable I/O Delay Settings in the Quartus II Software (ver 1.2, Mar 2008, 365 KB)
- AN 428: MAX II CPLD Design Guidelines (ver 1.1, Dec 2007, 425 KB)
- Designing With Low-Level Primitives User Guide (ver 3.0, Mar 2007, 492 KB)
- AN 411: Understanding PLL Timing for Stratix II Devices (ver 1.0, Mar 2006, 1 MB)
Design Example 1 (279 KB)
Design Example 2 (233 KB)
Benchmarking and Design Migration Techniques
- AN 311: ASIC-to-FPGA Design Methodology and Guidelines (ver 3.1, Apr 2009, 286 KB)
- AN 307: Altera Design Flow for Xilinx Users (ver 6.2, Apr 2009, 3 MB)
an307_DesignExample.zip (4 KB)
- Comparing IP Integration Approaches for FPGA Implementation (ver 1.1, Feb 2008, 195 KB)
- Performing Equivalent Timing Analysis Between Altera TimeQuest and Xilinx Trace (ver 1.0, Nov 2007, 1 MB)
- FPGA Performance Benchmarking Methodology (ver 1.6, Aug 2007, 246 KB)
- AN 345: Altera Design Flow for Lattice Semiconductor Users (ver 1.1, Jan 2005, 581 KB)
- TB 84: Differences in Logic Utilization between Quartus II & Synplify Report Files (ver 1.0, Nov 2002, 107 KB)
SOPC Builder System Development
- Avalon Interface Specifications (ver 1.2, Apr 2009, 485 KB)
(Replaces "Avalon Memory-Mapped Interface Specification" and "Avalon Streaming Interface Specification")
- AN 346: Using the Nios II Configuration Controller Reference Designs (ver 1.2, Mar 2009, 793 KB)
- AN458: Alternative Nios II Boot Methods (ver 1.1, Sep 2008, 334 KB)
AN458 design example files (37 KB)
- Comparing IP Integration Approaches for FPGA Implementation (ver 1.1, Feb 2008, 195 KB)
- AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems (ver 1.1, Nov 2007, 386 KB)
- AN 398: Using DDR/DDR2 SDRAM With SOPC Builder (ver 1.1, Aug 2006, 775 KB)
Using Megafunctions
- Memory-Based Multiplier Megafunction User Guide (ALTMEMMULT) (ver 3.0, Jul 2008, 492 KB)
altmemmult_DesignExample_ex1.zip (81 KB)
altmemmult_msim.zip (20 KB)
- Error Correction Code Megafunctions User Guide (ALTECC_ENCODER and ALTECC_DECODER) (ver 2.0, Jun 2008, 607 KB)
DE1_altecc_encoder.zip (5 KB)
DE2_altecc_decoder.zip (6 KB)
- Complex Multiplier Megafunction User Guide (ALTMULT_COMPLEX) (ver 1.0, May 2008, 674 KB)
altmult_complex_DesignExample.zip (75 KB)
altmult_complex_msim.zip (35 KB)
- Divider Megafunction User Guide (LPM_DIVIDE) (ver 2.3, Apr 2009, 944 KB)
lpm_divide.zip (89 KB)
lpm_divide_msim.zip (15 KB)
- Floating-Point Megafunctions User Guide (ver 1.0, Mar 2009, 2 MB)
Design Examples and ModelSim Files (11 MB)
- Counter Megafunction User Guide (LPM_COUNTER) (ver 2.3, Jun 2007, 1 MB)
counter_example_msim.do (460 bytes)
counter_example.qar (54 KB)
counter_example.vo (26 KB)
counter_example.vt (6 KB)
- Absolute Value Megafunction User Guide (LPM_ABS) (ver 2.2, Apr 2007, 380 KB)
lpm_abs.zip (174 KB)
lpm_abs_msim.zip (4 KB)
- Accumulator Megafunction User Guide (ALTACCUMULATE) (ver 2.3, Apr 2007, 1 MB)
altaccumulate_msim.zip (16 KB)
altaccumulate_semi_complete.zip (6 KB)
- Parallel Adder Megafunction User Guide (PARALLEL_ADD) (ver 2.2, Mar 2007, 632 KB)
parallel_add.zip (4 KB)
parallel_add_msim.zip (10 KB)
- Multiplier-Adder Megafunction User Guide (ALTMULT_ADD) (ver 2.3, Mar 2007, 4 MB)
altmult_add_DesignExample_ex1.zip (196 KB)
altmult_add_DesignExample_ex2.zip (205 KB)
altmult_add_ex1_msim.zip (113 KB)
altmult_add_ex2_msim.zip (16 KB)
- Multiplier-Accumulator Megafunction User Guide (ALTMULT_ACCUM) (ver 3.2, Mar 2007, 2 MB)
altmult_accum_Design_Example.zip (117 KB)
altmult_accum_msim.zip (16 KB)
- Multiplier Megafunction User Guide (LPM_MULT) (ver 2.2, Mar 2007, 694 KB)
lpm_mult.zip (0 bytes)
lpm_mult_msim.zip (22 KB)
- Square Root Megafunction User Guide (ALTSQRT) (ver 2.2, Mar 2007, 475 KB)
altsqrt Design Example Files (111 KB)
altsqrt ModelSim Files (10 KB)
- Adder/Subtractor Megafunction User Guide (LPM_ADD_SUB) (ver 2.2, Mar 2007, 551 KB)
add_sub.zip (258 KB)
mult_adder_msim.zip (13 KB)
- Comparator Megafunction User Guide (LPM_COMPARE) (ver 2.2, Mar 2007, 567 KB)
lpm_compare_msim.zip (4 KB)
lpm_compare.zip (175 KB) - Automating DSP Simulation and Implementation of Military Sensor Systems (ver 1.0, Mar 2009, 373 KB)
- Viterbi Compiler User Guide (ver 9.0, Mar 2009, 654 KB)
- NCO MegaCore Function User Guide (ver 9.0, Mar 2009, 1 MB)
- FFT MegaCore Function User Guide (ver 9.0, Mar 2009, 952 KB)
- CIC MegaCore Function User Guide (ver 9.0, Mar 2009, 1 MB)
- Reed-Solomon Compiler User Guide (ver 9.0, Mar 2009, 547 KB)
- Data (DQ) and Data Strobe (DQS) Megafunction User Guide (ALTDQ and ALTDQS) (ver 1.0, Dec 2008, 2 MB)
altdq_dqs_DesignExample.zip (67 KB)
altdq_dqs_msim.zip (11 KB)
- ALTDLL and ALTDQ_DQS Megafunctions User Guide (ver 2.0, Dec 2008, 5 MB)
ALTDLL_ALTDQ_DQS_DesignExample_ex1 (796 KB)
ALTDLL_ALTDQ_DQS_ex1_msim (397 KB)
- Phase-Locked Loops Reconfiguration Megafunction User Guide (ALTPLL_RECONFIG) (ver 4.0, Jul 2008, 7 MB)
altpll_reconfig_DesignExample1_ex1.zip (167 KB)
altpll_reconfig_DesignExample_ex2.zip (189 KB)
altpll_reconfig_DesignExample_ex3.zip (316 KB)
altpll_reconfig_ex1_msim.zip (68 KB)
altpll_reconfig_ex2_msim.zip (68 KB)
altpll_reconfig_ex3_msim.zip (432 KB)
- External Memory PHY Interface Megafunction User Guide (ALTMEMPHY) (ver 7.2, Jul 2009, 9 MB)
- SERDES Transmitter/Receiver Megafunction User Guide (ALTLVDS) (ver 5.0, Apr 2009, 925 KB)
altlvds_DesignExample.zip (203 KB)
altlvds_DesignExample_ex2.zip (113 KB)
altlvds_DesignExample_ex3.zip (252 KB)
altlvds_DesignExample_ex4.zip (37 KB)
altlvds_ex1_msim.zip (92 KB)
altlvds_ex2_msim.zip (58 KB)
altlvds_ex3_msim.zip (104 KB)
altlvds_ex4_msim.zip (433 KB)
- Remote Update Circuitry Megafunction User Guide (ALTREMOTE_UPDATE) (ver 2.4, Apr 2009, 928 KB)
altremote_update Design Example 1 (16 KB)
altremote_update Design Example 2 (16 KB)
altremote_update ModelSim Design Example 1 (12 KB)
altremote_update ModelSim Design Example 2 (12 KB)
- I/O Buffer Megafunction (ALTIOBUF) User Guide (ver 2.0, Dec 2008, 1 MB)
altiobuf_design_example_1.zip (56 KB)
altiobuf_ex1_msim.zip (91 KB)
- Phase-Locked Loops Megafunction User Guide (ALTPLL) (ver 7.0, Dec 2008, 829 KB)
ddr_clk.zip (98 KB)
ddr-clk-msim.zip (6 KB)
shift_clk.zip (387 KB)
shift_clk_msim.zip (10 KB)
- Active Serial Memory Interface Megafunction User Guide (ALTASMI_PARALLEL) (ver 2.4, Sep 2007, 775 KB)
- Double Data Rate I/O Megafunction User Guide (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) (ver 4.2, Jun 2007, 4 MB)
altddio_DesignExample_ex1.zip (112 KB)
altddio_DesignExample_ex2.zip (140 KB)
altddio_ex1_msim.zip (18 KB)
altddio_ex2_msim.zip (17 KB)
- Clock Control Block Megafunction User Guide (ALTCLKCTRL) (ver 2.4, Apr 2007, 337 KB)
altclkctrl Design Example (104 KB)
altclkctrl Design Example ModelSim (5 KB)
- Dynamic Calibrated On-Chip Termination Megafunction User Guide (ALTOCT) (ver 2.0, Dec 2006, 268 KB)
alt_oct_msim.zip (30 KB)
altoct_DesignExample.zip (30 KB)
- Flash Memory Megafunction User Guide (ver 2.0, Jul 2006, 1 MB)
alt_ufm Archive Files (72 KB)
alt_ufm ModelSim Files (16 KB) - HyperTransport MegaCore Function User Guide (ver 9.0, Mar 2009, 1 MB)
- DDR3 SDRAM High-Performance Controller User Guide (ver 9.0, Mar 2009, 864 KB)
- DDR and DDR2 SDRAM Controller Compiler User Guide (ver 9.0, Mar 2009, 2 MB)
- DDR and DDR2 SDRAM High-Performance Controller User Guide (ver 9.0, Mar 2009, 4 MB)
- ASI MegaCore Function User Guide (ver 9.0, Mar 2009, 464 KB)
- AN 370: Using the Serial FlashLoader With the Quartus II Software (ver 3.1, Apr 2009, 1 MB)
- AN 386: Using the Parallel Flash Loader with the Quartus II Software (ver 4.2, Apr 2009, 2 MB)
Flash Memory (873 bytes)
Nios Design (567 KB)
- Virtual JTAG (sld_virtual_jtag) Megafunction User Guide (ver 2.0, Dec 2008, 1 MB)
sld_virtual_jtag - Design Example 1 (140 KB)
sld_virtual_jtag - Design Example 2 (304 KB) - Shift Register (RAM-Based) Megafunction User Guide (ALTSHIFT_TAPS) (ver 2.0, Jul 2008, 438 KB)
DE_altshift_taps.zip (5 KB)
- RAM Initializer Megafunction User Guide (ALTMEM_INIT) (ver 1.0, May 2008, 524 KB)
DE1_internalROM.zip (8 KB)
DE2_externalROM.zip (10 KB)
- Single- and Dual-Clock FIFO Megafunction User Guide (ver 5.1, Feb 2009, 486 KB)
- Random Access Memory Megafunction User Guide (RAM) (ver 3.0, Dec 2008, 577 KB)
DesignExample_ram (11 KB)
- Shift Register Megafunction User Guide (LPM_SHIFTREG) (ver 3.0, Jan 2007, 939 KB)
lpm_shiftreg Design Files Archive Example 1 (84 KB)
lpm_shiftreg Design Files Example 1 (80 KB)
lpm_shiftreg Design Files Archive Example 2 (75 KB)
lpm_shiftreg Design Files Example 2 (70 KB)
lpm_shiftreg ModelSim Files Example 1 (5 KB)
lpm_shiftreg ModelSim Files Example 2 (4 KB)
- Flash Memory Megafunction User Guide (ver 2.0, Jul 2006, 1 MB)
alt_ufm Archive Files (72 KB)
alt_ufm ModelSim Files (16 KB)
- First-In-First-Out Partitioner Megafunction User Guide (FIFO Partitioner) (ver 1.2, Aug 2005, 306 KB)
Arithmetic
DSP
I/O
Interfaces
JTAG-Accessible Extensions
Memory Compiler
Programming Hardware
- USB Blaster Download Cable User Guide (ver 2.5, Apr 2009, 500 KB)
- EthernetBlaster Communications Cable User Guide (ver 1.1, Jul 2008, 1 MB)
- ByteBlaster II Download Cable User Guide (ver 1.4, Jul 2008, 295 KB)
- MasterBlaster Serial/USB Communications Cable User Guide (ver 1.1, Jul 2008, 222 KB)
- ByteBlasterMV Download Cable User Guide (ver 1.0, Aug 2004, 400 KB)
Other Related Documentation
- AN 370: Using the Serial FlashLoader With the Quartus II Software (ver 3.1, Apr 2009, 1 MB)
- AN 433: Constraining and Analyzing Source-Synchronous Interfaces (ver 2.0, Dec 2007, 1 MB)
- Video and image processing solutions for military applications (ver 2.0, Jun 2009, 278 KB)
- AN 453: HardCopy II Fitting Techniques (ver 2.0, Nov 2008, 716 KB)
- AN 549: Managing Designs with Multiple FPGAs (ver 1.0, Sep 2008, 776 KB)
- Increasing Productivity With Quartus II Incremental Compilation (ver 1.0, May 2008, 169 KB)
- FPGA Power Management and Modeling Techniques (ver 1.0, Nov 2007, 696 KB)
- AN 437: Power Optimization in Stratix III FPGAs (ver 2.0, Aug 2007, 219 KB)
