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资料： Stratix IV 器件
文档资料
功耗和热量处理
一般器件文件
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- Chapter 1. Stratix IV Device Family Overview (ver 1.1, Jul 2008, 198 KB)
- Chapter 2. Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices (ver 1.0, May 2008, 208 KB)
- Chapter 3. TriMatrix Embedded Memory Blocks in Stratix IV Devices (ver 1.0, May 2008, 273 KB)
- Chapter 4. DSP Blocks in Stratix IV Devices (ver 1.0, May 2008, 345 KB)
- Chapter 5. Clock Networks and PLLs in Stratix IV Devices (ver 1.0, May 2008, 625 KB)
- Chapter 9. Hot Socketing and Power-On Reset in Stratix IV Devices (ver 1.0, May 2008, 93 KB)
- Chapter 10. Configuration, Design Security, Remote System Upgrades with Stratix IV Devices (ver 1.0, May 2008, 773 KB)
- Chapter 11. SEU Mitigation in Stratix IV Devices (ver 1.0, May 2008, 210 KB)
- Chapter 12. JTAG Boundary Scan Testing (ver 1.0, May 2008, 110 KB)
- Chapter 13. Power Management in Stratix IV Devices (ver 1.0, May 2008, 137 KB)
Related Documentation
- AN 408: DDR2 Memory Interface Termination, Drive Strength, Loading, and Design Layout Guidelines (ver 2.1, Jul 2008, 4 MB)
SII Simulation Example (3 KB)
SIII Simulation Example (3 KB)
- AN 435: Using DDR and DDR2 SDRAM with Stratix III and Stratix IV Devices (ver 2.0, Aug 2008, 2 MB)
AN 435 Design Files (3 MB)
- AN 436: Using DDR3 SDRAM with Stratix III and Stratix IV Devices (ver 3.0, Aug 2008, 2 MB)
AN 436 Design Files (3 MB)
- AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III Devices (ver 1.1, Jul 2008, 1 MB)
Design Example for AN 461 (2 MB)
- AN 520: DDR3 SDRAM Memory Interface Termination and Layout Guidelines (ver 1.0, Jun 2008, 918 KB)
- External DDR Memory PHY Interface Megafunction User Guide (ALTMEMPHY) (ver 5.0, Jul 2008, 2 MB)
- Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers (ver 1.0, May 2008, 3 MB)
- AN 514: Power Optimization in Stratix IV FPGAs (ver 1.0, May 2008, 221 KB)
- Power Delivery Network (PDN) Tool User Guide (ver 1.0, May 2008, 963 KB)
Power Delivery Network (PDN) Tool (1 MB)
- PowerPlay Early Power Estimator User Guide For Stratix III and Stratix IV FPGAs (ver 2.0, May 2008, 1 MB)
- Stratix III and Stratix IV PowerPlay Early Power Estimator (ver 8.0 SP1.1, Aug 2008, 18 KB)
PowerPlay Early Power Estimator User Guide For Stratix III and Stratix IV FPGAs (1 MB)
- Stratix IV FPGA Power Management and Advantages (ver 1.0, May 2008, 2 MB)
- AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing (ver 1.0, May 2008, 1 MB)
- AN 529: Via Optimization Techniques for High-Speed Channel Designs (ver 1.0, May 2008, 690 KB)
- AN 530: Optimizing Impedence Discontinuity Caused by Surface Mount Pads for High-Speed Channel Designs (ver 1.0, May 2008, 208 KB)
- PCI Express Compiler User Guide (ver 8.0, May 2008, 2 MB)
- Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers (ver 1.0, May 2008, 3 MB)
- AN 520: DDR3 SDRAM Memory Interface Termination and Layout Guidelines (ver 1.0, Jun 2008, 918 KB)
- PCI Express hard intellectual property solutions from Altera (ver 1.0, Jul 2008, 165 KB)
- Triple Speed Ethernet MegaCore Function User Guide (ver 8.0, May 2008, 1 MB)
- 40-nm FPGAs and the Defense Electronic Design Organization (ver 1.0, Jul 2008, 313 KB)
- Anti-Tamper Capabilities in FPGA Designs (ver 1.0, Jul 2008, 310 KB)
- DO-254 Support for FPGA Design Flows (ver 1.0, Jul 2008, 91 KB)
- DO-254-certifiable IP cores (ver 1.0, Jul 2008, 85 KB)
- HardCopy ASICs (ver 1.1, Jul 2008, 277 KB)
- Military Benefits of the Managed Risk Process at 40 nm (ver 1.0, Jul 2008, 993 KB)
- Military Productivity Factors in Large FPGA Designs (ver 1.0, Jul 2008, 443 KB)
- think AND not OR - Altera at 40 nm brochure (ver 1.1, Jul 2008, 372 KB)
- Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers (ver 1.0, May 2008, 3 MB)
- HardCopy ASICs (ver 1.1, Jul 2008, 277 KB)
- Leveraging the 40-nm Process Node to Deliver the World's Most Advanced Custom Logic Devices (ver 1.0, May 2008, 371 KB)
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