中文版文档资料
- 白皮书：采用FPGA以及图像和传感器处理IP实现低功耗EO/IR系统开发
- 白皮书：采用FPGA业界第一种精度可调体系结构实现高精度DSP应用
- 白皮书：在28-nm 拓展收发器领先优势
- 白皮书：介绍28 nm 创新技术，超越摩尔定律
- 白皮书：在28-nm FPGA 上实现100-Gbit OTN 复用转发器解决方案
- 白皮书：在28-nm FPGA 上实现集成100-GbE 交换解决方案
- 白皮书：通过28-nm FPGA 解决100-GbE 线路卡设计挑战
- Stratix V FPGA系列封装和I/O选择指南
- Altera的28-nm高功效收发器
- Stratix V FPGA：为带宽而打造
英文版文档资料
Stratix V Device Handbook (13 MB)
Stratix V Device Handbook, Volume 1 (ver 1.0, Jul 2010, 8 MB)
Chapter 1. Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices (ver 1.0, Jul 2010, 668 KB) - Chapter 2. Memory Blocks in Stratix V Devices (ver 1.0, Jul 2010, 793 KB)
- Chapter 3. Variable Precision DSP Blocks in Stratix V Devices (ver 1.0, Jul 2010, 696 KB)
- Chapter 4. Clock Networks and PLLs in Stratix V Devices (ver 1.0, Jul 2010, 1 MB)
- Chapter 5. I/O Features in Stratix V Devices (ver 1.1, Jul 2010, 992 KB)
- Chapter 6. High-Speed Differential I/O Interfaces and DPA in Stratix V Devices (ver 1.0, Jul 2010, 1 MB)
- Chapter 7. External Memory Interfaces in Stratix V Devices (ver 1.0, Jul 2010, 643 KB)
- Chapter 8. Hot Socketing and Power-On Reset in Stratix V Devices (ver 1.0, Jul 2010, 171 KB)
- Chapter 9. Configuration, Design Security, and Remote System Upgrades in Stratix V Devices (ver 1.0, Jul 2010, 2 MB)
- Chapter 10. SEU Mitigation in Stratix V Devices (ver 1.0, Jul 2010, 206 KB)
- Chapter 11. JTAG Boundary-Scan Testing in Stratix V Devices (ver 1.0, Jul 2010, 174 KB)
- Chapter 12. Power Management in Stratix V Devices (ver 1.0, Jul 2010, 138 KB)
Section I. Device Core (3 MB)
Section II. I/O Interfaces (3 MB)
Section III. System Integration (2 MB)
Stratix V Device Handbook, Volume 2 (ver 1.0, Jul 2010, 4 MB)
- Chapter 1. Transceiver Architecture in Stratix V Devices (ver 1.1, Jul 2010, 1 MB)
- Chapter 2. Transceiver Clocking in Stratix V Devices (ver 1.0, Jul 2010, 1,000 KB)
- Chapter 3. Transceiver Reset Control in Stratix V Devices (ver 1.0, Jul 2010, 153 KB)
- Chapter 4. Transceiver Protocol Configurations in Stratix V Devices (ver 1.0, Jul 2010, 1 MB)
- Chapter 5. Custom Transceiver Configuration Datapath in Stratix V Devices (ver 1.0, Jul 2010, 711 KB)
- Chapter 6. Loopback in Stratix V Devices (ver 1.0, Jul 2010, 146 KB)
- Chapter 7. Dynamic Reconfiguration in Stratix V Devices (ver 1.0, Jul 2010, 118 KB)
Stratix V Device Handbook, Volume 3 (ver 1.0, Jul 2010, 489 KB)
- Chapter 1. DC and Switching Characteristics for Stratix V Devices (ver 1.0, Jul 2010, 457 KB)
Related Documentation
External Memory Interfaces
- Boosting System Performance with External Memory Solutions (ver 1.0, Jun 2010, 404 KB)
Power and Thermal Management
- Stratix III, Stratix IV, Stratix V, HardCopy III and HardCopy IV PowerPlay Early Power Estimator (ver 10.0SP1, Aug 2010, 7 KB)
PowerPlay Early Power Estimator User Guide (1 MB)
DSP
- Accelerating DSP Designs with the Total 28-nm DSP Portfolio (ver 1.0, Jul 2010, 810 KB)
- Stratix V FPGAs: Built for Bandwidth (ver 3.0, Jul 2010, 529 KB)
Design Guidelines
- Enhancing Robust SEU Mitigation with 28-nm FPGAs (ver 1.0, Jul 2010, 373 KB)
End Applications
- Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs (ver 1.1, Jul 2010, 881 KB)
- Enabling 100-Gbit OTN Muxponder Solutions on 28-nm FPGAs (ver 1.0, Apr 2010, 342 KB)
- Fulfilling Technology Needs for 40G–100G Network-Centric Operations and Warfare (ver 1.0, Sep 2010, 511 KB)
- Integrating 100-GbE Switching Solutions on 28-nm FPGAs (ver 1.1, Jul 2010, 623 KB)
- Stratix V FPGAs: Built for Bandwidth (ver 3.0, Jul 2010, 529 KB)
General Device Documentation
- Introducing Innovations at 28 nm to Move Beyond Moore’s Law (ver 1.1, Jul 2010, 1 MB)
- Enabling High-Precision DSP Applications with the FPGA Industry’s First Variable-Precision Architecture (ver 1.0, May 2010, 916 KB)
- Extending Transceiver Leadership at 28 nm (ver 1.0, May 2010, 939 KB)
- Increasing Design Functionality with Partial and Dynamic Reconfiguration in 28-nm FPGAs (ver 1.0, Jul 2010, 460 KB)
- Stratix V FPGA Family Package and I/O Selector Guide (ver 2.0, Aug 2010, 222 KB)
- Stratix V FPGAs: Built for Bandwidth (ver 3.0, Jul 2010, 529 KB)
