FPGAs & Structured ASICs: New Solutions for Changing Market Dynamics
by Ro Chawla, Senior Manager, HardCopy Business Development, Altera Corporation
Q1 2006 Issue
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Verifying a design using state-of-the-art 90-nm FPGAs for prototyping reduces risk. The risk can be further reduced by migrating FPGA-verified design into structured ASICs.
Today's system companies looking to implement new ideas in integrated circuits are faced with several challenges, including higher upfront costs, increased risk due to higher design complexity, and shrinking market windows. Traditional technology choices have included cell-based ASICs, application ASSPs, FPGAs, or microprocessors and digital signal processors. While each of these technologies has its own pros and cons, standard cell ASICs have historically been the best option in the production phase of a design providing the lowest unit production costs and lowest power consumption for system design.
However, designing a standard cell ASIC at today's 90-nm technology node is both an expensive and risky development proposition. Non-recurring engineering (NRE) costs, including cost of mask-sets, and engineering design efforts such as layout and verification, continue to rise as designs migrate to manufacturing technologies using smaller process geometries. In fact, the total development cost of a single complex, high-density standard cell ASIC at the 90-nm process node can easily be in the $20-30 million range (see Figure 1).
Figure 1. Increasing Costs Limit Access to 90/65-nm Design Development
Getting a device functioning correctly the first time is imperative to avoid additional costs and delays associated with re-spinning the ASIC. Simulation, verification, and validation of a design must be performed to ensure that the ASIC design is correct both before tape-out and after silicon has been received. Re-spins pose serious problems, not only increasing costs of engineering and mask-sets, but also from a lost market opportunity perspective. According to International Business Strategies, being 3 to 12 months late to market with a product can result in a potential sales loss ranging from 27 to 91 percent, respectively (see Table 1).
| Table 1. Time-to-Market Matters |
| Time-To-Market |
Potential Sales Achieved |
| First-To-Market |
100% |
| 3 Months Late |
73% |
| 6 Months Late |
53% |
| 9 Months Late |
32% |
| 12 Months Late |
9% |
These increased costs and high design risks are forcing designers to perform a more thorough return on investment (ROI) analysis to justify these expenses, which usually demands significant unit volumes be shipped to ensure an acceptable return. For example, if a company spends 20 percent of its estimated revenue on research and development for a 90-nm, high-density standard cell ASIC, for example $30 million, then the revenue from the device would have to hit $150 million per year. A single device rarely has more than a 10 percent market share, which means that a total market size of $1.5 billion would be required to ensure an acceptable ROI.
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