Condensing Avalon PIOs to Achieve Timing
by Jarrod Blackburn, Embedded Applications Engineer, Altera Corporation
Q1 2006 Issue
Achieving timing in systems that contain many Avalon® parallel input/output (PIO) components connecting to a single master can be difficult. The performance drop is usually due to the wide multiplexers created for masters capable of read operations. To increase the performance of the system, condense multiple PIO components into a single component thereby reducing the read master multiplexer width. Using Component Editor, which is available from SOPC Builder, it is possible to condense components with minimal system design changes.
To create a condensed PIO component, the following three building blocks are necessary: a register file, a decoder, and a multiplexer. The register file is the logical grouping of the individual PIO components and is enabled by the decoder. The decoder is enabled by the Avalon write signal and produces an enable bit for each PIO in the register file using the Avalon address. The multiplexer selects the appropriate PIO from the register file using the Avalon address. These three building blocks create a bus structure to connect external logic into the embedded system so bandwidth must be considered before grouping the components.
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