Enabling Clock Latency
by Minh Mac, Senior Applications Engineer, Altera Corporation
Q1 2006 Issue
Turning on this option enables support for clock latency in the Quartus® II Timing Analyzer. You can view latency on a clock as a simple delay on the clock path, which affects clock skew and not the setup and hold relationships. This is in contrast to an offset, which instead alters the setup and hold relationship between two clocks. The primary changes seen by turning on Clock Latency support are: Early and Late Clock Latency assignments will be honored; The compensation delay of a phase-locked loop (PLL) is analyzed as latency; The automatically computed offset is treated as latency for clock settings where you have not specified an offset.
To access this option in the graphical user interface, from the Assignments menu, choose Settings. On the Timing Requirements & Options page of the Settings dialog box, click More Settings. You can apply the option using a Tcl command with the global assignment ENABLE_CLOCK_LATENCY.
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