Speed Optimization Technique for Clock Domains
by Jennifer Stephenson, Senior Applications Engineer, Altera Corporation
Q1 2006 Issue
When using Quartus® II integrated synthesis, you can set the Speed Optimization Technique for Clock Domains logic option to specify that all combinational logic in or between specified clock domain(s) is optimized for speed. When you set this option on a particular clock signal, all the logic in this clock domain is optimized for speed during synthesis. The remainder of the design in other clock domains is synthesized with the project-wide Optimization Technique that is set in the Analysis & Synthesis Settings. You can also set the option from one clock to another clock signal, in which case the logic in paths from registers in the first clock domain to registers in the second clock domain are synthesized for speed.
To apply this option in the graphical user interface, from the Assignments menu, open the Assignment Editor. You can apply the option using tool command language (Tcl) commands with the instance assignment SYNTH_CRITICAL_CLOCK.
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