Rapid Chip, Rapid Chip Development
by Altium
Q1 2006 Issue
Page 1 of 2
More than any other single factor, the emergence of low-cost, high-capacity FPGAs is having a huge impact on the business of designing electronic products. More than 60 percent of board design turns include at least one CPLD or FPGA, and this figure is escalating. The successful integration of large-scale FPGAs with the boards they reside on requires engineers to think differently about the design process. Design tool vendors must rise to the challenge of automating this integration across traditionally disparate phases of the design process.
The Changing Role of FPGAs
Programmable logic is not only claiming an increasing amount of printed circuit board (PCB) real estate, but the role that programmable design is playing within both product development and the end-products is also changing. Engineers are fast discovering the programmability (and potential re-configurability) benefits these devices provide, both during the design process and even after product delivery.
As the price/density threshold continues to drop, FPGAs provide an obvious alternative systems-development platform without the astronomical non-recurring engineering (NRE) and tooling costs imposed by ASIC design flows. Additionally, the capacities of the new generations of FPGAs coming onto the market provide vast development platforms that engineers can use to migrate more system functionality from the PCB into the programmable environment of the FPGA.
Using FPGAs as a system platform has some compelling benefits, not the least of which is rapid chip development cycles. But time saved in the development of the FPGA circuitry does not automatically translate to faster time-to-market for the end product. When you deal with devices that can have upward of 1,000 pins, most of which are user-configurable, there are significant problems associated with incorporating them onto a PCB and connecting to off-chip devices. This issue can negate much of the time saved in the FPGA development stage.
Propagating Data Between the FPGA & PCB
Today's typical FPGA-PCB design flows comprise an "over-the-wall" approach to propagating design data. In general, the FPGA designer locks certain signals to specific pins during the development of programmable logic. The remainder of the pins are assigned by the FPGA place-and-route tools. The pin mapping is then "thrown over the wall" to the PCB designers who use this to create their board schematics.
Of course, little or no consideration is given to board routing issues during the initial pin definition. The result is that the board designer is left with a sub-optimal solution that can potentially lead to adding more PCB layers, increasing both PCB design time and the cost of the final board.
Because the transfer of pin information between FPGA and PCB design tools is currently mostly a manual process, there is limited scope for the board designers to make major changes to the FPGA pin map. The difficulty associated with transferring these changes between the FPGA and PCB tools often overrides the gains.
Synchronization is the Key
To overcome the difficulties involved in managing the integration of large-scale FPGAs onto a PCB, the process of data propagation must be automated. Automatic data propagation requires a high degree of integration between the FPGA development tools and the PCB design tools, with the aim of allowing I/O changes to be freely flowed between the two design realms.
The first step in this integration is to create a link between the output of the FPGA place-and-route process and the board-level schematic representation of the programmed FPGA that is used to define the PCB design connectivity. This link enables the transfer of all relevant pin information to the board-level schematics. The board design tool then uses this information to drive both the PCB layout and routing process, as well as feeding into board-level signal integrity analysis of the board with the programmed FPGA using the pin models supplied by the FPGA vendors.
The next step is to make this data flow bidirectional by allowing for the board designer to automatically flow pin changes back into the FPGA design. This bidirectional data exchange is critical to achieving any level of concurrency in the FPGA and board design processes.
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