When FPGA I/O Design Becomes a Necessity
by Rick Stroot, ISD Technical Marketing Manager, Mentor Graphics
Q1 2006 Issue
Page 1 of 2
Programmable logic devices (PLDs) are increasingly attractive for new design starts, as complex devices incorporating embedded processors, memory blocks, and digital signal processing (DSP) functions are now replacing entire ASICs. Design starts using ASICs have plummeted from a high of over 11,000 in 1997 to below 4,000 in 2003 (Source: Gartner Dataquest). Design starts have declined because FPGA architectures not only provide excellent reprogrammability, reduced risk, and lower development cost benefits compared to ASICs, but also enable quicker design turnarounds with a sufficiently competitive edge in the market and minimal performance compromise. New device families have shortened programming intervals by dedicating several general-purpose I/O pins to create wider configuration buses that then revert back to their primary I/O functionality. However, rising device complexities imply high pin counts, which creates new challenges and higher costs when integrating these devices on the printed circuit board (PCB). Design teams must implement urgent changes now to unite their HDL, FPGA, and PCB flows and thus ensure that they do not negate the cost and time-to-market advantages of using programmable logic.
This article details how Mentor Graphics® and Altera's combined flow overcome these challenges. The flow is based on Mentor Graphics I/O Designer and the Altera Quartus® II software in conjunction with the FPGA Xchange file format that allows the two tools to communicate.
Description
During the process of integrating FPGAs onto their boards, designers typically spend a considerable amount of time on planning an optimal FPGA pin-out (I/O design) to fit the requirements of both the FPGA and PCB. When tasked with the I/O design, engineers typically create an Altera® Quartus II Settings File (.qsf) using a text editor to fix the pin locations during the place-and-route process. The PCB designer on the other hand uses the same source of information to create the connections on the board-level schematic.
Mentor Graphics I/O Designer in combination with the new FPGA Xchange file (supported by Altera) simplifies the entire process by automating the creation of the pin constraint locations and writing them to the FPGA Xchange format. The same FPGA Xchange file is also used as a report file that is read by I/O Designer to use the same pin locations in the board-level schematic. Every change that is made to these pin assignments is kept consistent since I/O Designer positions itself between the FPGA and PCB flow communicating all changes made at either side.
Figure 1 shows the steps necessary to create and update the FPGA Xchange file from I/O Designer and the Quartus II software.
Figure 1. FPGA-PCB Design Flow
The flow, as shown in Figure 1, contains the following steps:
- The HDL design is started, and once the top-level entity is defined, it can be read into I/O Designer.
- A functional block symbol can be generated from the HDL.
- The schematic designer can now connect the functional block symbol to the rest of the board schematic. In parallel, the FPGA design is completed, simulated, and synthesized while at the same time both FPGA and PCB designers share the task of planning the I/O inside I/O Designer.
- Once the I/O design is complete (partially), the results are exported from I/O Designer to the Quartus II software via the FPGA Xchange file.
- Quartus II place-and-route uses the pin assignments in the FPGA Xchange file as a basis for the locations.
- When place-and-route is completed the final assignment, I/O standards and swap information are written back to the FPGA Xchange file again where I/O Designer picks up the changes.
- Then I/O Designer is ready to create a set of PCB symbols and place them onto a hierarchical schematic underneath the functional symbol that was generated earlier. The schematic design is then ready to be forwarded to Expedition layout.
- During PCB layout, you can swap the pins according to the swap rules defined inside I/O Designer.
- To ensure that the pins are swapped accordingly inside the FPGA, the information about these swapped pins is back annotated from Layout to the schematic where I/O Designer picks up the changes.
- Once the swap information is back into I/O Designer, the FPGA Xchange file is updated to re-run the Altera place-and-route process to ensure that the FPGA implementation is updated.
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