Synplify DSP Unleashes Potential of FPGA-Based DSPs
by Chris Eddington, Senior Technical Marketing Manager, DSP Products, Synplicity
Q1 2006 Issue
Page 1 of 3
Over the last 10 years, the FPGA industry has played a leading role in the explosion of high-performance digital signal processing (DSP) applications such as wireless communications, radar imaging, broadcast video, and consumer/automotive multimedia. Most of these applications simply require too much processing power to be implemented in a standalone digital signal processor, hence the major appeal of using FPGAs in these products. Now, as vendors drive towards 65-nm production and a wider range of price/performance across product lines, continued improvements in the DSP design flow is critical to the success of vendors and customers in these markets.
The Synplify® DSP product from Synplicity addresses this challenge by offering a true DSP synthesis methodology. The Synplify DSP tool drastically improves time-to-market and speeds design exploration by synthesizing register transfer level (RTL) implementations from a Simulink algorithm description. Using the Synplify DSP tool's Simulink library and a rich set of simulation and analysis tools, DSP architects can create and verify their algorithm, freeze the design, and then "synthesize" multiple RTL implementations with varying combinations of target devices, and timing and area constraints. This type of rapid design exploration speeds the design flow, ensures convergence on an optimal design, and significantly improves design portability across product generations.
The combination of Altera's FPGA-based DSP solutions and the Synplify DSP software gives design teams a significant advantage in their efforts to deliver competitive products to market quickly. This article discusses the challenges of the typical design flow used by many of today's DSP designers and provides a detailed illustration of the Synplify DSP flow and its advantages.
Implementation Challenges
Designers face challenges in their efforts to realize DSP-based systems. DSP architects are very adept at crafting DSP algorithms, and less so at developing the HDL code that drives custom IC implementation. Many are put off by the prospect of having to acquire unique coding skills just to transform their DSP designs into RTL code.
Yet another issue that has impeded designers from embracing custom DSP solutions is lack of implementation flexibility. Conventional methodologies have locked a designer into a specific architecture and/or library very early in the design process. In such a scenario, the effort to migrate that design to future applications or re-target to a different family of arrays can be monumental.
For these reasons, designers that are attempting to develop systems requiring digital processing elements can try to opt for standard processors instead of their more optimized and higher performance custom counterparts. But with the specialized DSP and performance capabilities of such devices as Altera's Stratix® II and CycloneTM II FPGAs, developers that avoid these options are doing so at the expense of the competitiveness of their systems. The high-density Stratix II family features embedded DSP blocks; high bandwidths; dedicated multipliers, pipeline and accumulate circuitry; and high-performance operation up to 450 MHz. The low-cost Cyclone arrays offer a cost-effective solution that includes embedded multipliers and other features tailored for DSP applications. The advantages of the FPGA approach can be significant, with benchmarks showing that the Altera arrays outperform the most widely-used standard processors by a ratio of 10:1.
Design Capture in the Synplify DSP Tool
The Synplify DSP software offers improvements in the design flow for DSP algorithms. The design environment is based on The MathWorks' Simulink/MATLAB framework, and the Synplify DSP tool provides a comprehensive library as a starting point for the algorithm designer. The first advantage that the designer appreciates is the rapid "time-to-simulation," which quickly and easily allows designers to use the library and begin simulation of a model. Because the Synplify DSP tool is a synthesis technology, the library elements such as fast Fourier transfers (FFTs) and filters are free from hardware or architecture-specific details making it much easier to configure and connect them for operation. No core generation steps or choices for area or performance-optimized architectures exist (area and timing optimization is offered later in the flow). The designer also does not have to worry about connecting global resets, clocks, and enables—this task is automatically taken care of during the implementation phase (although local enable and resets are available as options).
Another noticeable advantage is the simulation speed. The Synplify DSP library leverages the native fixed-point formats of Simulink and therefore runs very near the full speed of the simulation engine.
The Synplify DSP software also leverages the data format and sample rate displays of Simulink so the designer can see how the data path size and sample rates are configured in a single view. For example, Figure 1 shows a GSM digital down converter design which makes several rate and data format changes from input to output. The input is the fasted rate shown in red with 14-bit signed fractional fixed-point format, which feeds into a mixer followed by 18-bit CIC and 16-bit downsampling filters. Each color shows where the rate changes happen and the fixed-point formats are clearly labeled. All Synplify DSP library components support these features.
Figure 1. GSM Digital Down Converter Design Showing Data Formats & Sample Rates
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