Best Practices: Image Processing Design & Verification
by Vanteon
Q1 2006 Issue
Recent leaps in FPGA density and performance, as well as the availability of intellectual property (IP) blocks and soft processors such as the Altera® Nios® II processor, have enabled designers to fit ever more features into a single system-on-programmable-chip. The board-level integration stage is far too late and inefficient of a time to begin verifying the logic design and identifying defects. Simulation has become an absolute necessity for large, complex FPGA designs; yet hardware description languages (HDLs) provide very little in the way of high-level semantics for abstraction, data analysis, and visualization.
To address this burgeoning complexity and the shortcomings of HDL-based verification, Vanteon has created JVerify®, a Java-based platform for performing high-level functional verification of complex HDL designs. JVerify provides a rich API that allows intelligent testbenches to be created in Java, using object-oriented techniques. Rather than developing numerous HDL test cases using copy-and-paste, JVerify allows engineers to craft a single testbench using multiple layers of abstraction, each supplying the system with the knowledge to stimulate and automatically test a single facet of the overall design under test (DUT). Multiple threads of control are used to concurrently drive and monitor DUT interfaces, while constrained randomization can be employed to supplement traditional directed test cases. Individual test cases simply inherit from the master testbench class, setting parameters for stimulus, and performing any actions that are truly unique to the test.
Regardless of test complexity, or the use of randomization, determinism is always preserved; given the same randomization seed, a test case produces the same results on every run. Event and error logging is centralized in one or more log files, each entry stamped with the simulation time. A test summary provides at-a-glance pass/fail indication, and tests can be batched for regression runs prior to major releases of functionality. As the design and the testbench code evolve, so does the entire suite of tests. When defects are found, testbench code is written to automatically detect the failure and log an error. By virtue of a JVerify testbench's object-oriented nature, every test ever created against the design automatically inherits the ability to check for the failure mode, even if a test's original author had not been thinking about possible interactions with the failing subsystem. Once the defect has been fixed in the design's HDL code, the testbench retains its knowledge of the failure mode, ready to raise a red flag if it ever manifests itself again.
While the JVerify methodology of automated verification alone can reap great rewards in efficiency, it is capable of enabling yet more productivity. Since both the design stimulus and response data flow through a Java program, domain-specific frameworks can be created which leverage the rich APIs inherently provided by the Java 2 platform. To exemplify the power of this approach, Vanteon has created a framework for video and image processing which allows engineers and other stakeholders to subjectively evaluate the performance of an FPGA-based image-processing pipeline before even committing to a board design.
Figure 1 shows a screen shot of the framework in operation. Once the simulation is launched, a Java control panel appears, prompting the user to select an image file (.gif, .jpg, or .png) to stimulate the design. Controls are provided allowing the user to select any arbitrary region of the image. In addition, hooks are provided to embed algorithm-specific sub-panels into the GUI, allowing the user to set parameters.
Figure 1. Vanteon Image Processing Framework
In Figure 1, the system being simulated consists of a convolution window generator and a bilinear scaling kernel. Both of these synthesizable IP cores, as well as others, have been developed by Vanteon and are licensed free-of-charge for use in their clients' designs. Once the user clicks Start Test, the simulation is allowed to advance. As lines of processed video egress from the design, they are displayed in pseudo real time alongside the original image.
In migrating an image-processing algorithm from a high-level description to an actual, pipelined implementation on an FPGA, many decisions must be made. Numerical representation and precision, buffering requirements, processing frequency versus pixel rate, color depth, and many more represent dimensions of control which must strike a balance between performance, device utilization, and power consumption. Being able to see and subjectively evaluate the impact of each change upon algorithm output can be invaluable early on in the design process, when critical decisions about device family, size, and speed grade must be made. In addition, the direct visual feedback from the simulated design represents a tremendous advantage when debugging visual artifacts arising from defects in the processing kernel. Without this framework, engineers must manually go through raw data waveforms or text files to see if they have been able to reproduce a failure in simulation. Visual defects that are very obvious on a display, such as a patch of data being incorrectly addressed out of a buffer, can be a needle in the proverbial haystack of seemingly random image data. Viewed in Vanteon's JVerify-enabled image processing framework, however, such defects are easily identified and located with coordinates, allowing the engineer to rapidly work backwards to the offending logic.
The FPGA technology available today represents a wealth of opportunities for companies to create innovative new products that boast both the unparalleled performance of custom hardware and the flexibility of re-programmability. Altera's Stratix® and CycloneTM device families provide a solid foundation for implementing complex image processing algorithms, at a variety of combinations of price and performance. The combination of Altera's lineup of FPGA devices and Vanteon's experience in crafting custom image-processing solutions translate into an unbeatable advantage for your next design challenge.
For more information contact Vanteon at request_info@vanteon.com or at (888) 506-5677.
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