Optimize System Flexibility by Integrating Custom Microprocessors Into FPGAs
by Martin Won, Altera Corporation
Bob Palmero, Bob Oglesby & Tim Dunn, Host Automation
Peter Foy, Arrow Electronics
Jim Millener & Ivan Kotzig, Toolrama
Q1 2006 Issue
Page 1 of 3
Microprocessors and microcontrollers are some of the most ubiquitous components in digital electronic systems. However, despite the large number of vendors and offerings available for these components, embedded system designers are often challenged to find the exact processor or microcontroller that will fit their need. This difficulty arises mainly from the fact that, for many applications, no commercial off-the-shelf (COTS) product provides an optimal combination of performance, peripherals (both type and number), price, packaging, and persistence (life cycle). As a result, embedded systems designers often make compromises in their choices of these components.
Programmable-logic-based soft-core processors like the Altera® Nios® II embedded processor overcome the limitations of COTS processors and microcontrollers by enabling users to specify and only pay for the exact functionality they require. Nios II processor users often customize the type and number of peripherals, an easy modification with the available development tools. This article documents two examples of first-time Nios II processor users who initially chose Altera's soft-core processors to overcome the inflexibility of COTS microprocessors and microcontrollers. Their success with these projects led them to adopt the Nios II processor as their processor of choice for similar projects going forward, shortening their time-to-market, increasing their product differentiation, and providing a number of other benefits.
Nios II Processor Overview
Altera's Nios II family of embedded processors features a general-purpose RISC CPU architecture designed to address a wide range of embedded applications. The Nios II processor family consists of three cores—fast (Nios II/f), economy (Nios II/e), and standard (Nios II/s) cores—each optimized for a specific price and performance range. All three cores share a common 32-bit instruction set architecture (ISA) and are 100 percent binary code-compatible. Designers can easily add Nios II processors to their systems by using the SOPC Builder tool included in Altera's tool for programmable logic design, the Quartus® II design software.
Nios II processors use an interface bus called the Avalon® switch fabric, which provides a set of pre-defined signal types with which a user can easily connect additional functions such as peripherals, memory interfaces, and other Nios II processors. With user input, Altera's SOPC Builder system development tool automatically generates the Avalon switch fabric logic. The Avalon switch fabric logic includes capabilities for data-path multiplexing, address decoding, wait-state generation, dynamic-bus sizing, interrupt-priority assigning, slave-side arbitration, multi-processor systems, and advanced switch fabric transfers.
Nios II processors and their associated Avalon switch fabric are implemented using the programmable logic resources in Altera FPGAs, such as the CycloneTM and Stratix® series devices. These FPGAs offer the logic and memory resources needed to create highly integrated, customized systems within a single device. The smallest of Altera's FPGAs can implement single-processor designs, and the largest can host hundreds of Nios II processors. Table 1 shows the logic available in Cyclone and Stratix series devices measured in logic elements (LEs), the basic building block of Altera FPGAs, and the logic required for each of the three Nios II cores.
| Table 1. Nios II Processor Logic Utilization in Various Altera Device Families |
| Device Family |
Available LEs Across Entire Family |
Nios II/f Logic Utilization (LEs) |
Nios II/s Logic Utilization (LEs) |
Nios II/e Logic Utilization (LEs) |
| Stratix II |
15,600 - 179,400 |
1,723 |
1,286 |
603 |
| Stratix |
10,570 - 79,040 |
1,808 |
1,170 |
529 |
| Cyclone II |
4,608 - 68,416 |
1,595 |
1,033 |
542 |
| Cyclone |
2,910 - 20,060 |
1,679 |
1,145 |
522 |
Table 2 lists the DMIPS for a Nios II processor design implemented in Altera Stratix and Cyclone series devices with the following elements:
- Fast version of Nios II processor (Nios II/f processor, version 1.01)
- JTAG UART
- 64-Kbyte on-chip memory (Cyclone designs use 1 Mbyte of off-chip SDRAM)
| Table 2. Nios II Processor Performance in Altera Device Families |
| Device Family |
Device Speed Grade (1) |
Nios II/f Performance (DMIPS) |
Nios II/s Performance (DMIPS) |
Nios II/e Performance (DMIPS) |
| Stratix II |
-3 |
225 |
133 |
31 |
| Stratix |
-5 |
157 |
99 |
23 |
| Cyclone II |
-6 |
105 |
57 |
22 |
| Cyclone |
-6 |
101 |
57 |
16 |
Note to Table 2:
- The fastest speed grade offered in each family. DMIPS reported were obtained using the Dhrystone benchmark version 2.1.
COTS Processor Inflexibility, Need for Greater Capability Force Change
When the right combination of peripherals, packaging, price, performance, and other features are not available in any single COTS processor, embedded designers often rely on additional external devices, including discrete and/or programmable logic, to implement the needed functionality. The Nios II processor enables embedded designers to avoid this situation by allowing the designer to easily integrate the processor and any desired peripherals into a single device. The experience of two companies, Toolrama, a developer of automotive diagnostic and performance equipment, and Host Automation, a developer of hardware for industrial programmable logic controllers (PLCs), demonstrates how Altera's Nios II processor delivers these and other significant advantages over COTS processors.
Toolrama's first experience with Altera's soft-core processor solution came during their project to upgrade their DiabloSport Predator, a high-performance tuning flash programmer. The Predator is used to advance a vehicle's timing and optimize the air/fuel ratio, as well as remap the transmission shift points in automatic transmissions. The goal of the upgrade was to add support for a larger LCD with more attractive graphics, provide TCP/IP connectivity, add a USB port, and change from SRAM to less expensive SDRAM. The prior Predator design used a 32-bit Motorola processor, but upgrading to a higher-end Motorola processor required to support these additional features would have resulted in non-competitive pricing for the Predator.
In Host Automation's case, the project that led them to choose the Altera solution was a 100Base-T Ethernet controller for a PLC. This was a natural extension of their prior products, which included one of the first 10Base-T Ethernet controller interfaces for a PLC and also fiber optic-based Ethernet PLC communications modules. Host Automation needed a custom interface from the processor to a proprietary PLC backplane (a common feature of a PLC), and a small package to occupy as little board space as possible on the 3.2" × 2.5" printed circuit board. After spending two years researching and developing prototypes that used ARM7-based processors and a TI processor, Host Automation concluded that there was no COTS processor that would meet their requirements, including their performance, package, life cycle, and cost targets.
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