Ensuring Serial Protocol Signal Integrity with FPGAs & Embedded Transceivers
by Bob Blake, Product Line Manager, Transceiver Products, Altera Corporation
Q1 2006 Issue
Page 1 of 3
Today's high-end FPGAs with embedded transceivers support a variety of widely accepted serial protocol standards, including Gigabit Ethernet, PCI Express, XAUI, and the Serial RapidIOTM standard. Maintaining signal integrity is a key element for the successful implementation of these standards within high bandwidth applications. This can be particularly difficult, however, because of the peculiar characteristics of printed circuit boards (PCBs} which will deteriorate signal quality. FPGAs with built-in transceivers provide adjustable dynamic pre-emphasis, equalization, and output voltage controls to help overcome signal deterioration on PCBs, delivering excellent signal integrity.
Unfortunately, ensuring signal integrity is about to become even more challenging as design requirements and next generation protocols lift data transfer rates higher. In essence, transceivers will have to operate between 155 Mbps and 11.1 Gbps to support current applications. In reviewing today's transceiver marketplace, some adjustments are needed in transceiver design to ensure signal integrity via effective jitter performance, while maintaining a robust, low power, and economically viable solution.
Overcoming Board Losses
Transceivers have become commonplace in many applications across all markets, from broadcast, test and measurement, and storage, to the more established wireless and networking applications. This drive, fueled by the desire to move more data, is supplemented by the emergence of many new transmission protocols.
Despite widespread acceptance, however, transceivers bring some complexity of their own. Obviously all board interconnects are transmission lines, but at lower data rates transmission line effects have little influence on signal integrity or the ability for the signal to correctly transmit and receive. However, as the speed increases or, more importantly, as the signal edge rates increase, transmission line characteristics become more relevant. Poor termination, badly placed traces, or discontinuities in connector or board vias will deteriorate the signal. You can overcome many of these issues by using on-chip termination, careful board layout, and good quality connectors. Although as data rates rise, these issues require more and more design effort.
One key area which cannot be controlled purely by board layout is high-frequency signal attenuation or losses caused by the PCB itself. The high-frequency losses cause data dependant jitter (also known as inter-symbol interference) prevents the signal from reaching its full strength within its symbol time, causing it to spread into the next signal. This high-frequency attenuation is created by two key functions: skin effect and dielectric loss.
Transceivers tend to include additional circuitry in the buffer to overcome high frequency attenuation. This circuitry modifies the signal to allow the data to be interpreted correctly. At the transmitter, pre-emphasis (also known as de-emphasis by some protocols standards bodies) is used to help overcome the problem. Pre-emphasis boosts the strength of the first symbol sent after a transition in the data level (either 1 to 0 or 0 to 1), basically adding high-frequency components back into the waveform.
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