// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.1 Internal Build 150 04/05/2007 SJ Full Version"

// DATE "05/02/2007 15:45:43"

// 
// Device: Altera EP1S10F780C5 Package FBGA780
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module counter_example (
	cout,
	clock,
	reset);
output 	[8:0] cout;
input 	clock;
input 	reset;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \clock~combout ;
wire \reset~combout ;
wire [8:0] \inst|lpm_counter_component|auto_generated|safe_q ;


check_counter inst(
	.safe_q_8(\inst|lpm_counter_component|auto_generated|safe_q [8]),
	.safe_q_7(\inst|lpm_counter_component|auto_generated|safe_q [7]),
	.safe_q_6(\inst|lpm_counter_component|auto_generated|safe_q [6]),
	.safe_q_5(\inst|lpm_counter_component|auto_generated|safe_q [5]),
	.safe_q_4(\inst|lpm_counter_component|auto_generated|safe_q [4]),
	.safe_q_3(\inst|lpm_counter_component|auto_generated|safe_q [3]),
	.safe_q_2(\inst|lpm_counter_component|auto_generated|safe_q [2]),
	.safe_q_1(\inst|lpm_counter_component|auto_generated|safe_q [1]),
	.safe_q_0(\inst|lpm_counter_component|auto_generated|safe_q [0]),
	.clock(\clock~combout ),
	.reset(\reset~combout ),
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

// atom is at PIN_R25
stratix_io \clock~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clock~combout ),
	.regout(),
	.ddioregout(),
	.padio(clock),
	.dqsundelayedout());
// synopsys translate_off
defparam \clock~I .ddio_mode = "none";
defparam \clock~I .input_async_reset = "none";
defparam \clock~I .input_power_up = "low";
defparam \clock~I .input_register_mode = "none";
defparam \clock~I .input_sync_reset = "none";
defparam \clock~I .oe_async_reset = "none";
defparam \clock~I .oe_power_up = "low";
defparam \clock~I .oe_register_mode = "none";
defparam \clock~I .oe_sync_reset = "none";
defparam \clock~I .operation_mode = "input";
defparam \clock~I .output_async_reset = "none";
defparam \clock~I .output_power_up = "low";
defparam \clock~I .output_register_mode = "none";
defparam \clock~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_R27
stratix_io \reset~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\reset~combout ),
	.regout(),
	.ddioregout(),
	.padio(reset),
	.dqsundelayedout());
// synopsys translate_off
defparam \reset~I .ddio_mode = "none";
defparam \reset~I .input_async_reset = "none";
defparam \reset~I .input_power_up = "low";
defparam \reset~I .input_register_mode = "none";
defparam \reset~I .input_sync_reset = "none";
defparam \reset~I .oe_async_reset = "none";
defparam \reset~I .oe_power_up = "low";
defparam \reset~I .oe_register_mode = "none";
defparam \reset~I .oe_sync_reset = "none";
defparam \reset~I .operation_mode = "input";
defparam \reset~I .output_async_reset = "none";
defparam \reset~I .output_power_up = "low";
defparam \reset~I .output_register_mode = "none";
defparam \reset~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_J17
stratix_io \cout[8]~I (
	.datain(\inst|lpm_counter_component|auto_generated|safe_q [8]),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(cout[8]),
	.dqsundelayedout());
// synopsys translate_off
defparam \cout[8]~I .ddio_mode = "none";
defparam \cout[8]~I .input_async_reset = "none";
defparam \cout[8]~I .input_power_up = "low";
defparam \cout[8]~I .input_register_mode = "none";
defparam \cout[8]~I .input_sync_reset = "none";
defparam \cout[8]~I .oe_async_reset = "none";
defparam \cout[8]~I .oe_power_up = "low";
defparam \cout[8]~I .oe_register_mode = "none";
defparam \cout[8]~I .oe_sync_reset = "none";
defparam \cout[8]~I .operation_mode = "output";
defparam \cout[8]~I .output_async_reset = "none";
defparam \cout[8]~I .output_power_up = "low";
defparam \cout[8]~I .output_register_mode = "none";
defparam \cout[8]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_K16
stratix_io \cout[7]~I (
	.datain(\inst|lpm_counter_component|auto_generated|safe_q [7]),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(cout[7]),
	.dqsundelayedout());
// synopsys translate_off
defparam \cout[7]~I .ddio_mode = "none";
defparam \cout[7]~I .input_async_reset = "none";
defparam \cout[7]~I .input_power_up = "low";
defparam \cout[7]~I .input_register_mode = "none";
defparam \cout[7]~I .input_sync_reset = "none";
defparam \cout[7]~I .oe_async_reset = "none";
defparam \cout[7]~I .oe_power_up = "low";
defparam \cout[7]~I .oe_register_mode = "none";
defparam \cout[7]~I .oe_sync_reset = "none";
defparam \cout[7]~I .operation_mode = "output";
defparam \cout[7]~I .output_async_reset = "none";
defparam \cout[7]~I .output_power_up = "low";
defparam \cout[7]~I .output_register_mode = "none";
defparam \cout[7]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_C15
stratix_io \cout[6]~I (
	.datain(\inst|lpm_counter_component|auto_generated|safe_q [6]),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(cout[6]),
	.dqsundelayedout());
// synopsys translate_off
defparam \cout[6]~I .ddio_mode = "none";
defparam \cout[6]~I .input_async_reset = "none";
defparam \cout[6]~I .input_power_up = "low";
defparam \cout[6]~I .input_register_mode = "none";
defparam \cout[6]~I .input_sync_reset = "none";
defparam \cout[6]~I .oe_async_reset = "none";
defparam \cout[6]~I .oe_power_up = "low";
defparam \cout[6]~I .oe_register_mode = "none";
defparam \cout[6]~I .oe_sync_reset = "none";
defparam \cout[6]~I .operation_mode = "output";
defparam \cout[6]~I .output_async_reset = "none";
defparam \cout[6]~I .output_power_up = "low";
defparam \cout[6]~I .output_register_mode = "none";
defparam \cout[6]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_E15
stratix_io \cout[5]~I (
	.datain(\inst|lpm_counter_component|auto_generated|safe_q [5]),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(cout[5]),
	.dqsundelayedout());
// synopsys translate_off
defparam \cout[5]~I .ddio_mode = "none";
defparam \cout[5]~I .input_async_reset = "none";
defparam \cout[5]~I .input_power_up = "low";
defparam \cout[5]~I .input_register_mode = "none";
defparam \cout[5]~I .input_sync_reset = "none";
defparam \cout[5]~I .oe_async_reset = "none";
defparam \cout[5]~I .oe_power_up = "low";
defparam \cout[5]~I .oe_register_mode = "none";
defparam \cout[5]~I .oe_sync_reset = "none";
defparam \cout[5]~I .operation_mode = "output";
defparam \cout[5]~I .output_async_reset = "none";
defparam \cout[5]~I .output_power_up = "low";
defparam \cout[5]~I .output_register_mode = "none";
defparam \cout[5]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_H14
stratix_io \cout[4]~I (
	.datain(\inst|lpm_counter_component|auto_generated|safe_q [4]),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(cout[4]),
	.dqsundelayedout());
// synopsys translate_off
defparam \cout[4]~I .ddio_mode = "none";
defparam \cout[4]~I .input_async_reset = "none";
defparam \cout[4]~I .input_power_up = "low";
defparam \cout[4]~I .input_register_mode = "none";
defparam \cout[4]~I .input_sync_reset = "none";
defparam \cout[4]~I .oe_async_reset = "none";
defparam \cout[4]~I .oe_power_up = "low";
defparam \cout[4]~I .oe_register_mode = "none";
defparam \cout[4]~I .oe_sync_reset = "none";
defparam \cout[4]~I .operation_mode = "output";
defparam \cout[4]~I .output_async_reset = "none";
defparam \cout[4]~I .output_power_up = "low";
defparam \cout[4]~I .output_register_mode = "none";
defparam \cout[4]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_B15
stratix_io \cout[3]~I (
	.datain(\inst|lpm_counter_component|auto_generated|safe_q [3]),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(cout[3]),
	.dqsundelayedout());
// synopsys translate_off
defparam \cout[3]~I .ddio_mode = "none";
defparam \cout[3]~I .input_async_reset = "none";
defparam \cout[3]~I .input_power_up = "low";
defparam \cout[3]~I .input_register_mode = "none";
defparam \cout[3]~I .input_sync_reset = "none";
defparam \cout[3]~I .oe_async_reset = "none";
defparam \cout[3]~I .oe_power_up = "low";
defparam \cout[3]~I .oe_register_mode = "none";
defparam \cout[3]~I .oe_sync_reset = "none";
defparam \cout[3]~I .operation_mode = "output";
defparam \cout[3]~I .output_async_reset = "none";
defparam \cout[3]~I .output_power_up = "low";
defparam \cout[3]~I .output_register_mode = "none";
defparam \cout[3]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_K15
stratix_io \cout[2]~I (
	.datain(\inst|lpm_counter_component|auto_generated|safe_q [2]),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(cout[2]),
	.dqsundelayedout());
// synopsys translate_off
defparam \cout[2]~I .ddio_mode = "none";
defparam \cout[2]~I .input_async_reset = "none";
defparam \cout[2]~I .input_power_up = "low";
defparam \cout[2]~I .input_register_mode = "none";
defparam \cout[2]~I .input_sync_reset = "none";
defparam \cout[2]~I .oe_async_reset = "none";
defparam \cout[2]~I .oe_power_up = "low";
defparam \cout[2]~I .oe_register_mode = "none";
defparam \cout[2]~I .oe_sync_reset = "none";
defparam \cout[2]~I .operation_mode = "output";
defparam \cout[2]~I .output_async_reset = "none";
defparam \cout[2]~I .output_power_up = "low";
defparam \cout[2]~I .output_register_mode = "none";
defparam \cout[2]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_L17
stratix_io \cout[1]~I (
	.datain(\inst|lpm_counter_component|auto_generated|safe_q [1]),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(cout[1]),
	.dqsundelayedout());
// synopsys translate_off
defparam \cout[1]~I .ddio_mode = "none";
defparam \cout[1]~I .input_async_reset = "none";
defparam \cout[1]~I .input_power_up = "low";
defparam \cout[1]~I .input_register_mode = "none";
defparam \cout[1]~I .input_sync_reset = "none";
defparam \cout[1]~I .oe_async_reset = "none";
defparam \cout[1]~I .oe_power_up = "low";
defparam \cout[1]~I .oe_register_mode = "none";
defparam \cout[1]~I .oe_sync_reset = "none";
defparam \cout[1]~I .operation_mode = "output";
defparam \cout[1]~I .output_async_reset = "none";
defparam \cout[1]~I .output_power_up = "low";
defparam \cout[1]~I .output_register_mode = "none";
defparam \cout[1]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_J16
stratix_io \cout[0]~I (
	.datain(\inst|lpm_counter_component|auto_generated|safe_q [0]),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(cout[0]),
	.dqsundelayedout());
// synopsys translate_off
defparam \cout[0]~I .ddio_mode = "none";
defparam \cout[0]~I .input_async_reset = "none";
defparam \cout[0]~I .input_power_up = "low";
defparam \cout[0]~I .input_register_mode = "none";
defparam \cout[0]~I .input_sync_reset = "none";
defparam \cout[0]~I .oe_async_reset = "none";
defparam \cout[0]~I .oe_power_up = "low";
defparam \cout[0]~I .oe_register_mode = "none";
defparam \cout[0]~I .oe_sync_reset = "none";
defparam \cout[0]~I .operation_mode = "output";
defparam \cout[0]~I .output_async_reset = "none";
defparam \cout[0]~I .output_power_up = "low";
defparam \cout[0]~I .output_register_mode = "none";
defparam \cout[0]~I .output_sync_reset = "none";
// synopsys translate_on

endmodule

module check_counter (
	safe_q_8,
	safe_q_7,
	safe_q_6,
	safe_q_5,
	safe_q_4,
	safe_q_3,
	safe_q_2,
	safe_q_1,
	safe_q_0,
	clock,
	reset,
	devpor,
	devclrn,
	devoe);
output 	safe_q_8;
output 	safe_q_7;
output 	safe_q_6;
output 	safe_q_5;
output 	safe_q_4;
output 	safe_q_3;
output 	safe_q_2;
output 	safe_q_1;
output 	safe_q_0;
input 	clock;
input 	reset;
input 	devpor;
input 	devclrn;
input 	devoe;

wire gnd = 1'b0;
wire vcc = 1'b1;



lpm_counter lpm_counter_component(
	.q({safe_q_8,safe_q_7,safe_q_6,safe_q_5,safe_q_4,safe_q_3,safe_q_2,safe_q_1,safe_q_0}),
	.clock(clock),
	.aclr(reset),
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

endmodule

module lpm_counter (
	q,
	clock,
	aclr,
	devpor,
	devclrn,
	devoe);
output 	[8:0] q;
input 	clock;
input 	aclr;
input 	devpor;
input 	devclrn;
input 	devoe;

wire gnd = 1'b0;
wire vcc = 1'b1;



cntr_ash auto_generated(
	.q({q[8],q[7],q[6],q[5],q[4],q[3],q[2],q[1],q[0]}),
	.clock(clock),
	.aclr(aclr),
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

endmodule

module cntr_ash (
	q,
	clock,
	aclr,
	devpor,
	devclrn,
	devoe);
output 	[8:0] q;
input 	clock;
input 	aclr;
input 	devpor;
input 	devclrn;
input 	devoe;

wire gnd = 1'b0;
wire vcc = 1'b1;

wire \counter_cella7~COUT ;
wire \counter_cella7~COUTCOUT1 ;
wire \counter_cella6~COUT ;
wire \counter_cella6~COUTCOUT1 ;
wire \counter_cella5~COUT ;
wire \counter_cella5~COUTCOUT1 ;
wire \counter_cella4~COUT ;
wire \counter_cella3~COUT ;
wire \counter_cella3~COUTCOUT1 ;
wire \counter_cella2~COUT ;
wire \counter_cella2~COUTCOUT1 ;
wire \counter_cella1~COUT ;
wire \counter_cella1~COUTCOUT1 ;
wire \counter_cella0~COUT ;
wire \counter_cella0~COUTCOUT1 ;


// atom is at LC_X23_Y30_N8
stratix_lcell counter_cella8(
// Equation(s):
// q[8] = DFFEAS((!\counter_cella4~COUT  & \counter_cella7~COUT ) # (\counter_cella4~COUT  & \counter_cella7~COUTCOUT1 ) $ !q[8], GLOBAL(\clock~combout ), !GLOBAL(\reset~combout ), , , , , , )

	.clk(clock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(q[8]),
	.aclr(aclr),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(\counter_cella4~COUT ),
	.cin0(\counter_cella7~COUT ),
	.cin1(\counter_cella7~COUTCOUT1 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(q[8]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam counter_cella8.cin0_used = "true";
defparam counter_cella8.cin1_used = "true";
defparam counter_cella8.cin_used = "true";
defparam counter_cella8.lut_mask = "f00f";
defparam counter_cella8.operation_mode = "normal";
defparam counter_cella8.output_mode = "reg_only";
defparam counter_cella8.register_cascade_mode = "off";
defparam counter_cella8.sum_lutc_input = "cin";
defparam counter_cella8.synch_mode = "off";
// synopsys translate_on

// atom is at LC_X23_Y30_N7
stratix_lcell counter_cella7(
// Equation(s):
// q[7] = DFFEAS(q[7] $ ((!\counter_cella4~COUT  & \counter_cella6~COUT ) # (\counter_cella4~COUT  & \counter_cella6~COUTCOUT1 )), GLOBAL(\clock~combout ), !GLOBAL(\reset~combout ), , , , , , )
// \counter_cella7~COUT  = CARRY(!\counter_cella6~COUT  # !q[7])
// \counter_cella7~COUTCOUT1  = CARRY(!\counter_cella6~COUTCOUT1  # !q[7])

	.clk(clock),
	.dataa(q[7]),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(aclr),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(\counter_cella4~COUT ),
	.cin0(\counter_cella6~COUT ),
	.cin1(\counter_cella6~COUTCOUT1 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(q[7]),
	.cout(),
	.cout0(\counter_cella7~COUT ),
	.cout1(\counter_cella7~COUTCOUT1 ));
// synopsys translate_off
defparam counter_cella7.cin0_used = "true";
defparam counter_cella7.cin1_used = "true";
defparam counter_cella7.cin_used = "true";
defparam counter_cella7.lut_mask = "5a5f";
defparam counter_cella7.operation_mode = "arithmetic";
defparam counter_cella7.output_mode = "reg_only";
defparam counter_cella7.register_cascade_mode = "off";
defparam counter_cella7.sum_lutc_input = "cin";
defparam counter_cella7.synch_mode = "off";
// synopsys translate_on

// atom is at LC_X23_Y30_N6
stratix_lcell counter_cella6(
// Equation(s):
// q[6] = DFFEAS(q[6] $ !(!\counter_cella4~COUT  & \counter_cella5~COUT ) # (\counter_cella4~COUT  & \counter_cella5~COUTCOUT1 ), GLOBAL(\clock~combout ), !GLOBAL(\reset~combout ), , , , , , )
// \counter_cella6~COUT  = CARRY(q[6] & !\counter_cella5~COUT )
// \counter_cella6~COUTCOUT1  = CARRY(q[6] & !\counter_cella5~COUTCOUT1 )

	.clk(clock),
	.dataa(vcc),
	.datab(q[6]),
	.datac(vcc),
	.datad(vcc),
	.aclr(aclr),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(\counter_cella4~COUT ),
	.cin0(\counter_cella5~COUT ),
	.cin1(\counter_cella5~COUTCOUT1 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(q[6]),
	.cout(),
	.cout0(\counter_cella6~COUT ),
	.cout1(\counter_cella6~COUTCOUT1 ));
// synopsys translate_off
defparam counter_cella6.cin0_used = "true";
defparam counter_cella6.cin1_used = "true";
defparam counter_cella6.cin_used = "true";
defparam counter_cella6.lut_mask = "c30c";
defparam counter_cella6.operation_mode = "arithmetic";
defparam counter_cella6.output_mode = "reg_only";
defparam counter_cella6.register_cascade_mode = "off";
defparam counter_cella6.sum_lutc_input = "cin";
defparam counter_cella6.synch_mode = "off";
// synopsys translate_on

// atom is at LC_X23_Y30_N5
stratix_lcell counter_cella5(
// Equation(s):
// q[5] = DFFEAS(q[5] $ \counter_cella4~COUT , GLOBAL(\clock~combout ), !GLOBAL(\reset~combout ), , , , , , )
// \counter_cella5~COUT  = CARRY(!\counter_cella4~COUT  # !q[5])
// \counter_cella5~COUTCOUT1  = CARRY(!\counter_cella4~COUT  # !q[5])

	.clk(clock),
	.dataa(vcc),
	.datab(q[5]),
	.datac(vcc),
	.datad(vcc),
	.aclr(aclr),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(\counter_cella4~COUT ),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(q[5]),
	.cout(),
	.cout0(\counter_cella5~COUT ),
	.cout1(\counter_cella5~COUTCOUT1 ));
// synopsys translate_off
defparam counter_cella5.cin_used = "true";
defparam counter_cella5.lut_mask = "3c3f";
defparam counter_cella5.operation_mode = "arithmetic";
defparam counter_cella5.output_mode = "reg_only";
defparam counter_cella5.register_cascade_mode = "off";
defparam counter_cella5.sum_lutc_input = "cin";
defparam counter_cella5.synch_mode = "off";
// synopsys translate_on

// atom is at LC_X23_Y30_N4
stratix_lcell counter_cella4(
// Equation(s):
// q[4] = DFFEAS(q[4] $ (!\counter_cella3~COUT ), GLOBAL(\clock~combout ), !GLOBAL(\reset~combout ), , , , , , )
// \counter_cella4~COUT  = CARRY(q[4] & (!\counter_cella3~COUTCOUT1 ))

	.clk(clock),
	.dataa(q[4]),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(aclr),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\counter_cella3~COUT ),
	.cin1(\counter_cella3~COUTCOUT1 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(q[4]),
	.cout(\counter_cella4~COUT ),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam counter_cella4.cin0_used = "true";
defparam counter_cella4.cin1_used = "true";
defparam counter_cella4.lut_mask = "a50a";
defparam counter_cella4.operation_mode = "arithmetic";
defparam counter_cella4.output_mode = "reg_only";
defparam counter_cella4.register_cascade_mode = "off";
defparam counter_cella4.sum_lutc_input = "cin";
defparam counter_cella4.synch_mode = "off";
// synopsys translate_on

// atom is at LC_X23_Y30_N3
stratix_lcell counter_cella3(
// Equation(s):
// q[3] = DFFEAS(q[3] $ (\counter_cella2~COUT ), GLOBAL(\clock~combout ), !GLOBAL(\reset~combout ), , , , , , )
// \counter_cella3~COUT  = CARRY(!\counter_cella2~COUT  # !q[3])
// \counter_cella3~COUTCOUT1  = CARRY(!\counter_cella2~COUTCOUT1  # !q[3])

	.clk(clock),
	.dataa(q[3]),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(aclr),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\counter_cella2~COUT ),
	.cin1(\counter_cella2~COUTCOUT1 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(q[3]),
	.cout(),
	.cout0(\counter_cella3~COUT ),
	.cout1(\counter_cella3~COUTCOUT1 ));
// synopsys translate_off
defparam counter_cella3.cin0_used = "true";
defparam counter_cella3.cin1_used = "true";
defparam counter_cella3.lut_mask = "5a5f";
defparam counter_cella3.operation_mode = "arithmetic";
defparam counter_cella3.output_mode = "reg_only";
defparam counter_cella3.register_cascade_mode = "off";
defparam counter_cella3.sum_lutc_input = "cin";
defparam counter_cella3.synch_mode = "off";
// synopsys translate_on

// atom is at LC_X23_Y30_N2
stratix_lcell counter_cella2(
// Equation(s):
// q[2] = DFFEAS(q[2] $ (!\counter_cella1~COUT ), GLOBAL(\clock~combout ), !GLOBAL(\reset~combout ), , , , , , )
// \counter_cella2~COUT  = CARRY(q[2] & (!\counter_cella1~COUT ))
// \counter_cella2~COUTCOUT1  = CARRY(q[2] & (!\counter_cella1~COUTCOUT1 ))

	.clk(clock),
	.dataa(q[2]),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(aclr),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\counter_cella1~COUT ),
	.cin1(\counter_cella1~COUTCOUT1 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(q[2]),
	.cout(),
	.cout0(\counter_cella2~COUT ),
	.cout1(\counter_cella2~COUTCOUT1 ));
// synopsys translate_off
defparam counter_cella2.cin0_used = "true";
defparam counter_cella2.cin1_used = "true";
defparam counter_cella2.lut_mask = "a50a";
defparam counter_cella2.operation_mode = "arithmetic";
defparam counter_cella2.output_mode = "reg_only";
defparam counter_cella2.register_cascade_mode = "off";
defparam counter_cella2.sum_lutc_input = "cin";
defparam counter_cella2.synch_mode = "off";
// synopsys translate_on

// atom is at LC_X23_Y30_N1
stratix_lcell counter_cella1(
// Equation(s):
// q[1] = DFFEAS(q[1] $ \counter_cella0~COUT , GLOBAL(\clock~combout ), !GLOBAL(\reset~combout ), , , , , , )
// \counter_cella1~COUT  = CARRY(!\counter_cella0~COUT  # !q[1])
// \counter_cella1~COUTCOUT1  = CARRY(!\counter_cella0~COUTCOUT1  # !q[1])

	.clk(clock),
	.dataa(vcc),
	.datab(q[1]),
	.datac(vcc),
	.datad(vcc),
	.aclr(aclr),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\counter_cella0~COUT ),
	.cin1(\counter_cella0~COUTCOUT1 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(q[1]),
	.cout(),
	.cout0(\counter_cella1~COUT ),
	.cout1(\counter_cella1~COUTCOUT1 ));
// synopsys translate_off
defparam counter_cella1.cin0_used = "true";
defparam counter_cella1.cin1_used = "true";
defparam counter_cella1.lut_mask = "3c3f";
defparam counter_cella1.operation_mode = "arithmetic";
defparam counter_cella1.output_mode = "reg_only";
defparam counter_cella1.register_cascade_mode = "off";
defparam counter_cella1.sum_lutc_input = "cin";
defparam counter_cella1.synch_mode = "off";
// synopsys translate_on

// atom is at LC_X23_Y30_N0
stratix_lcell counter_cella0(
// Equation(s):
// q[0] = DFFEAS(!q[0], GLOBAL(\clock~combout ), !GLOBAL(\reset~combout ), , , , , , )
// \counter_cella0~COUT  = CARRY(q[0])
// \counter_cella0~COUTCOUT1  = CARRY(q[0])

	.clk(clock),
	.dataa(vcc),
	.datab(q[0]),
	.datac(vcc),
	.datad(vcc),
	.aclr(aclr),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(q[0]),
	.cout(),
	.cout0(\counter_cella0~COUT ),
	.cout1(\counter_cella0~COUTCOUT1 ));
// synopsys translate_off
defparam counter_cella0.lut_mask = "33cc";
defparam counter_cella0.operation_mode = "arithmetic";
defparam counter_cella0.output_mode = "reg_only";
defparam counter_cella0.register_cascade_mode = "off";
defparam counter_cella0.sum_lutc_input = "datac";
defparam counter_cella0.synch_mode = "off";
// synopsys translate_on

endmodule