Many system designers currently use multiple FLEX 10K, FLEX 6000, and MAX 7000 devices on the same board because each architecture is ideally suited for certain types of applications. Combining the benefits of the three families into one architecture permits designers to integrate a complex system into a single device, eliminating the need for multi-device modules, saving board space, and simplifying complex design implementation. This architectural breakthrough is the APEX MultiCore architecture, which combines and enhances the strengths of the FLEX 10K, FLEX 6000, and MAX 7000 architectures. Figure 1 summarizes the features of the APEX 20K device family, the ultimate in design flexibility and efficiency for high-performance, system-on-a-programmable-chip applications.
Figure 1. APEX 20K Device Features
Altera's revolutionary MultiCore embedded architecture is an innovative combination of three different types of PLD structures: look-up tables (LUTs), like those found in FLEX 10K and FLEX 6000 devices; product-term blocks, like those found in MAX 7000 devices; and enhanced embedded memory blocks, like those found in FLEX 10KE devices. See Figure 2. Together, these structures make the integration of complex functions, such as megafunctions, an easy and efficient process.
Figure 2. APEX MultiCore Architecture
The MultiCore architecture is made up of logic array blocks (LABs), each consisting of 10
The MultiCore architecture enhances the continuous metal FastTrack Interconnect routing structure by introducing a fourth level to the routing hierarchy. In addition to the global row and column interconnect, the MegaLAB interconnect connects all LABs and the ESB within a MegaLAB structure. It allows for increased performance by using local routing instead of global routing resources, as shown in Figure 3. A local interconnect also connects the LEs within the same LAB to adjacent LABs, as in the FLEX 6000 LAB interleaving.
Figure 3. MegaLAB & FastTrack Interconnect Routing Structures
Unlike other APEX devices, APEX 20KC devices feature an all-layer copper interconnect structure. All-layer copper interconnects use copper for all metal layers, optimizing the performance-critical high-speed interconnects typically found in metal layers 1 through 5. Considerable performance benefits are made possible using copper interconnects as they have lower resistance than aluminum interconnects.
Embedded System Block Capability
The ESB is the heart of the MultiCore architecture. Each ESB contains 2,048 programmable bits that can be configured as product-term logic, LUT-based logic or three types of memory: dual-port RAM, read-only memory (ROM), or content-addressable memory (CAM).
Embedded Product-Term Logic
Configuring the ESB for product-term logic provides a powerful level of integration that is unique to APEX devices. Product-term logic has historically been superior for control logic functions such as address decoding and state machines. The integrated product-term approach enables APEX devices to achieve maximum efficiency and performance for these functions. Each APEX ESB can be configured with up to 16 macrocells, similar to a streamlined subset of the MAX 7000 LAB. Each ESB can contain up to 32 product terms,
XORlogic, 16 D-flipflops, and parallel expanders.Embedded Dual-Port RAM
The APEX ESB supports the wide range of RAM widths and depths required in a system-level design and can be configured as 128 x 16, 256 x 8, 512 x 4, 1,024 x 2, or 2,048 x 1. ESBs can be easily cascaded together to form wider and deeper memories. Like the EAB of FLEX 10KE devices, the APEX ESB supports dual-port RAM with independent read/write ports, synchronous or asynchronous access, and 161 MHz first-in first-out (FIFO) buffer performance. APEX 20KE and APEX 20KC devices both support dual-port RAM. Table 1 shows how this system-level memory integration efficiently supports the various RAM requirements of a system-level design, such as cache RAM, dual-port FIFO buffers, or ROM.
Table 1. System-Level Memory Support Function Configuration Total ESBs Performance MHz Cache RAM 256 x 32
4,096 x 644
128161
150Dual-Port FIFO 128 x 32
128 x 642
4161
161ROM 256 x 32
4,096 x 644
128227
200Content Addressable Memory
CAM is a memory technology that accelerates search applications and is widely used in high-speed communication applications. Unlike RAM, which receives an address as input and outputs data, CAM takes a data input and outputs the address. Each
APEX ESB can be configured as a 32-word by 32-bit CAM, and multiple ESBs can be cascaded to support larger CAM blocks. APEX CAM, which can be configured in APEX 20KE and APEX 20KC devices, is faster than traditional discrete CAM because integrating the CAM into the PLD eliminates off- and on-chip delays. For more information, see the APEX CAM page.
Enhanced Phase-Locked Loop
The APEX phase-locked loop (PLL) offers enhanced ClockLock synchronization circuitry, with an extended output frequency range. APEX devices, which offer up to four PLLs per device, also support enhanced ClockBoost multiplication circuitry, offering m/(n x k) and m/(n x v) clock multiplication and ClockShift circuitry. For more information, see the APEX PLL page.
MultiVolt Interface
The trend toward higher system performance requirements and lower supply voltages makes it imperative that devices support multiple low-voltage I/O standards. APEX devices support the Altera MultiVolt I/O interface for 5-V, 3.3-V, 2.5-V, and 1.8-V devices. APEX 20KC and APEX 20KE devices support all four voltage interfaces; APEX 20K devices can interface with 5-V, 3.3-V, and 2.5-V devices.
Low-Voltage I/O Support
All APEX devices offer user-selectable I/O support for the LVTTL and LVCMOS standards(1). APEX 20KE and APEX 20KC devices also support the SSTL-2, SSTL-3, AGP, CTT, HSTL, GTL+, LVDS, and LVPECL standards. True-LVDS circuitry has been specifically incorporated in the APEX 20KC and APEX 20KE devices as a key high-performance I/O interface solution. More information on APEX I/O support can be found on the APEX I/O Support, APEX LVDS Support, and APEX True-LVDS Solution pages.
Note:
1. AGP: advanced graphics port; CTT: center tap terminated; GTL+: gunning transceiver logic; HSTL: high-speed transceiver logic; LVCMOS: low-voltage complementary metal-oxide semiconductor; LVPECL: low-voltage positive emitter-coupled logic; LVTTL: low-voltage transistor-transistor logic; PCI: peripheral component interconnect; SSTL: stub-series terminated logic
