APEX devices can interface with several types of memory.
DRAM
Dynamic random access memory (DRAM) requires refresh cycles due to existence of capacitors in each memory cell. Capacitors need to be charged or discharged to read or write data. The two most common types of DRAM are high-speed dynamic random access memory (SDRAM) and double data rate (DDR) DRAM.
SDRAM
Synchronous dynamic random access memory (SDRAM) is high-speed DRAM with a fully pipelined internal architecture and a synchronous interface. In SDRAM, the memory clock is synchronized with the processor clock, resulting in faster clock-to-data output times. This increases the number of instructions that the processor can perform in a given time, leading to extremely fast data rates. APEX devices interface with SDRAM memory to enhance system performance, and these devices comply with the PC-100 and PC-133 SDRAM specifications.
DDR
APEX devices interface with double data rate (DDR) SDRAM, a standard memory scheme for many communication applications. DDR technology allows an output on both the rising and falling edges of the clock, and addresses and control signals are registered at every positive clock edge. Designed to transfer two data words per clock cycle at the I/O pins, DDR SDRAM uses the DDR architecture to obtain high-speed operations.
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Unlike DRAM, static random access memory (SRAM) does not require refresh cycles, and data is stored in the memory cell as long as power remains. Quad data rate (QDR) and zero bus turnaround (ZBT) SRAMs are used in specific applications where clock-to-access time is critical.
QDR
Quad data rate (QDR) static random access memory (SRAM) uses separate read and write ports to run at DDR, which results in four data throughputs per clock cycle. QDR SRAMs are ideal for high-bandwidth applications where they serve as the main memory for look-up tables, linked lists, and controller buffer memory. APEX devices interface with QDR, standards for the QDR. The QDR consortium consists of Cypress Semiconductor, IDT, and Micron Technology.
ZBT
Zero bus turnaround (ZBT) SRAM is synchronous fast static RAM designed to eliminate dead bus cycles during back-to-back read/write and back-to-back write/read cycles by providing 100% bus utilization. IDT and Micron is a vendor for this type of ZBT; other memory vendors have different definitions of ZBT technology, such as Cypress (no bus latency, or NoBL), or Samsung and Toshiba (no turnaround RAM, or NtRAM). APEX™ devices interface with ZBT SRAM using the LVTTL I/O standard. By using ZBT, APEX devices allow maximum bus throughput for high-performance systems.
