Introduced in early 2001, APEX™ II FPGAs build on Altera's APEX 20KE and APEX 20KC devices to deliver the performance, density, and features needed for a comprehensive system-on-a-programmable-chip (SOPC) solution. The largest APEX II FPGA, the EP2A70 device, was the industry’s first FPGA to utilize a 0.13-µm all-layer-copper interconnect process. Today, Altera’s high-density Stratix™ FPGAs are manufactured on this advanced technology, and the new, high-density, high-performance Stratix II FPGAs are manufactured on a 90-nm all-layer-copper process. While designers wishing to leverage Altera’s more enhanced, highest-density, and highest-performance FPGA technology, can design with Stratix II FPGAs, Altera continues to support customers who have leveraged the APEX II device family.
The APEX II family supports multiple I/O protocols, allowing these devices to interface with other devices in a complex system. Processing-intensive data path functions that must be received and transmitted at high speeds can be easily implemented with one or multiple APEX II devices. Cutting-edge bus protocols and standards-such as POS-PHY Level 4, RapidIO™, UTOPIA IV and common switch interface (CSIX)-can be quickly implemented in APEX II devices, allowing high-speed communication with ASSPs, ASICs, and other FPGAs. In addition, APEX II devices combine a high-performance enhanced FPGA architecture with dedicated I/O circuitry for 1-Gbps LVDS.
With up to 67,200 logic elements (LEs) and 1.1 Mbits of embedded RAM, APEX II devices offer abundant logic resources and remarkable I/O performance. The all-layer-copper EP2A70 device maintains Altera’s leadership in offering designers large density devices with both increased core performance and a sustainable long-term, low-cost model. Figure 2 shows the EP2A70 device.
Figure 1. APEX II EP2A70 Device
APEX II devices can support True-LVDS™ data transfer rates of up to 1 Gbps on 36 channels and data bandwidths up to 366 Gbps. In conjunction with an extensive intellectual property (IP) portfolio, Altera's industry-leading Quartus® II software, which includes the LogicLock™ incremental design capability, unleashes the full potential of APEX II devices-and helps designers minimize cost, time-to-market, and overall design complexity.
There are more answers to common questions on the APEX II Questions & Answers page.
APEX II Enhanced Architecture
- APEX II Enhanced Architecture
- Up to 67,200 LEs and 1.1 Mbits of embedded RAM
- 1.5-V, 0.15-µm, 8-layer-metal, all-layer-copper process
- Support for up to eight global clock domains and four fast inputs
- Enhanced phase-locked loops (PLLs)
-
4-Kbit-embedded RAM with dual-port+ mode for embedded system blocks (ESBs) with bidirectional read and write ports
- Support for Nios® embedded processors—Altera's industry-leading soft-core embedded processor solutions
- True-LVDS™ Support
- 1 Gbps per channel
- LVDS, LVPECL, PCML, and HyperTransport™ technology
- Clock-data synchronization (CDS)
- 36 input and 36 output channels
- Flexible-LVDS™ Support
- LVDS, LVPECL, HyperTransport technology
- 624 Mbps per channel
- Up to 88 input and 88 output channels
Communication Protocol Support
- Host Processor Interfaces
- RapidIO
- HyperTransport
- PCI-X
- External Memory Interfaces
- Double data rate (DDR) SRAMs and SDRAMs
- Quad data rate (QDR) SRAMs
- Zero bus turnaround (ZBT) SRAMs
- DDR FCRAM
- Switch Fabric Interfaces
- CSIX
- PHY-Link Layer Interfaces
- UTOPIA IV
- POS-PHY Level 4
- Flexbus L4
