Enhanced APEX II Architecture
APEX™ II devices are FPGAs manufactured on Altera's industry leading 0.15-µm, all-layer-copper process with 8 layers of metal. The high-density, feature-rich APEX II architecture includes abundant logic element and embedded memory resources, high-performance clock networks, and enhanced phase-locked loops (PLLs).
High Density, High-Performance Devices
APEX II device densities range from 16,640 to 67,200 LEs and from 416 Kbits to 1.1 Mbits of embedded RAM. The APEX II architecture is designed for high performance and provides an enhanced feature set capable of supporting the latest and emerging standards and protocols.
All-Layer-Copper Process
APEX II devices are fabricated on an all-layer-copper process technology. Copper interconnects provide up to a 30% to 40% performance increase over traditional 0.18-µm aluminum interconnects on similar processes and inherently consume 20% less power.
Embedded System Blocks (ESBs)
Each 4-Kbit ESB is capable of Dual-Port+ mode, enabling bidirectional read and write ports based on independent clocks. Figure 1 illustrates the APEX II Dual-Port+ capability. ESBs can also be configured as high-performance content-addressable memory (CAM) to be used in fast search applications, as well as in first-in first-out (FIFO) buffers.
Figure 1: Dual-Port+ in APEX II Devices
Global Clock Networks
APEX II devices have eight low-skew global clock networks that are used to efficiently distribute clock signals throughout the device. Additionally, APEX II devices have four fast networks that can be driven by either clock or data signals, minimizing the detrimental effects of internal skew on high fan-out signals. Figure 2 shows the interaction between the global clock networks and PLLs in APEX II devices.
Figure 2: Global Clocks & PLLs in APEX II Devices
Enhanced PLLs
APEX II devices feature four general-purpose PLLs for advanced clock management functions and four additional LVDS PLLs, which are not shown in Figure 1, for high-speed serial transmission clock generation. General-purpose APEX II PLLs support ClockLock™, ClockBoost™ and ClockShift™ functionality. The ClockLock and ClockBoost features permit advanced clock manipulation, efficiently reducing the effects of external board delay and internal device skew while improving input/output performance. ClockShift circuitry allows designers to precisely shift clocks by 90º, 180º, or 270º in 0.5-ns increments. Table 1 summarizes the APEX II PLL capabilities.
| Table 1: APEX II PLL Capabilities |
|
Feature
|
APEX II Support
|
| PLLs |
4 |
| PLL Outputs |
2 per PLL (8 per device) |
| Global Clocks |
8 (1 per PLL output) |
| External Outputs |
2 |
| Frequency Range (MHz) |
Input: 1.5 to 160.0
Output: 15.0 to 420.0 |
| ClockBoost Circuitry |
Multiplication: 1x to 160x
Division: 1x to 256x
T1/E1 conversion: supported |
| ClockShift Circuitry |
Coarse: 90º, 180º, 270º
Fine: 0.5-ns resolution |
|
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