Altera® Excalibur™ devices contain powerful system-level features that offer unprecedented design flexibility, performance, and system integration that take system-on-a-programmable-chip (SOPC) designs to new levels. A comprehensive development flow and broad range of industry-standard development tools complete the support infrastructure for Excalibur FPGAs (see Table 1).
| Table 1. Excalibur Features & Benefits at a Glance | |
|---|---|
| Features | Benefits |
| Embedded Processor FPGA Integration |
Excalibur devices integrate a microprocessor subsystem with FPGA architecture to enable optimized, single-chip implementations of complex designs, and reduce the number of complex board components. This integration simplifies board layout, increases system reliability, and reduces power requirements and overall costs. In addition, integrating a processor, memory, memory interfaces, peripherals, and FPGA configuration logic on one device ensures that vital microprocessor functional blocks are available at boot-time without requiring FPGA configuration or valuable logic element (LE) resources in the FPGA or external components. Excalibur devices can boot from (external) flash memory and provide the flexibility required for real-time FPGA configuration. |
| SOPC Design Flow |
ASIC designs have typically been used to integrate microprocessors, intellectual property (IP) cores, and custom logic for system-on-chip (SOC) implementations. Cost-effective ASIC designs have often required long lead times for product delivery and verification, high minimum-order quantities, and large-volume shipment requirements. The Excalibur design methodology combines a microprocessor and an FPGA to address today's cost, integration, and lead-time issues. Excalibur devices can effectively lower the cost of entry into ASIC and SOC markets. Designers can use Excalibur devices and the SOPC Builder design flow to attain the performance benefits of SOC integration without the volume potentials of ASIC designs. |
| Dynamic Configuration |
Excalibur devices allow dynamic configuration of the FPGA while the processor is active for other tasks, such as running the operating system. Users can also alter device functionality via real-time changes to the system hardware (depending on the system's operating modes). By storing these configurable system functions in cost-effective, non-volatile memory, and using the processor to configure the hardware without the need to reboot, a smaller FPGA can perform the same tasks without the need to configure all functions simultaneously. |
| Design Partitioning |
Excalibur devices allow flexible partitioning of the hardware and software without changing the physical board design. Using SOPC Builder and the Quartus® II design software, a designer can configure and reconfigure a system to create the desired hardware platform. SOPC Builder also allows users to generate the required software for hardware configuration to address specific application needs. Excalibur devices also feature dynamic configuration that can balance the performance trade-offs between processors and FPGAs or software and Excalibur devices. Users can make changes at any time, and tune their systems for cost and performance trade-offs during the design phase. |
| Concept-to-System Design Flow |
A comprehensive set of Altera and industry-standard third-party developer tools support Excalibur devices. Using these tools, designers can take design implementations from concept to system in less than an hour, and in some cases, less than 15 minutes. Design support spans from the front-end (SOPC Builder-based integration of FPGA design, and software code generation) to the back-end (place-and-route mechanisms that pull together hardware and software outputs to run on Excalibur and other Altera FPGA devices). |
| SOPC Builder | SOPC Builder is a system integration tool that simplifies SOPC design by integrating the entire Excalibur development process. Through an intuitive graphical user interface (GUI) and the automation of SOPC development and integration, SOPC Builder enables designers to define an entire system in a fraction of the time of traditional SOC designs. SOPC Builder includes the Altera® Quartus II software, enabling FPGA designers to quickly and easily move from design concept to system implementation. |
| Developer Software | Altera provides a suite of developer software for Excalibur devices that support immediate code development right out of the box, including GNUPro Toolkit and a 45-day license for ARM® Developer Suite (ADS) Lite. |
| Development Kits |
Altera and its third-party partners provide a full line of Excalibur development kits that allow immediate, out-of-the-box development tools to get designs to market quickly. Each of these kits includes a development board and all of the hardware and software necessary to get users on their way toward completing system designs. These development kits are ideal platforms for software engineers to evaluate code on the Excalibur architecture. At the same time, the kits provide hardware engineers the flexibility to configure the appropriate systems for such evaluation. From time to time, Altera also offers special development kit promotions to its customers. |
