ARM922T Architecture
The embedded stripe in Excalibur™ devices integrates a 32-bit ARM922T™ processor with on-chip SRAM and dual-port SRAM memories, peripherals, and FPGA configuration logic. The processor can operate at up to 200 MHz (210 Dhrystone MIPS). The ARM922T processor includes 8 Kbytes of instruction and 8 Kbytes of data cache memory, and a memory management unit (MMU) for operating system support.
This page describes the processor and associated features:
ARM9TDMI Processor Core
The ARM922T processor is a high-performance, 32-bit embedded core with instruction set, debug, and math extensions. It uses a five-stage pipeline and a Harvard architecture (separate instruction and data paths) to achieve a performance ratio of 1.05 MIPS per MHz. The Harvard architecture simplifies the bus interface to the processor and provides high-performance processor implementations by separating data and instruction caches. The processor supports big and little Endian modes to suit the target system requirements for software coherency and operating system support. The ARM9TDMI processor core also has a task identifier register specifically designed for real-time operating system (RTOS) support.
For more information about the ARM9TDMI processor core, refer to the ARM9TDMI Technical Reference Manual.
ARM922T Processor
The ARM922T processor is one of several delivery mechanisms for the ARM9TDMI core. The processor contains 8 Kbytes of instruction and 8 Kbytes of data caches, along with associated memory management. Both caches have an eight word line length and are 64-way set-associative. The processor also includes a data write buffer and an AMBA bus interface, and provides the option for the ETM9™ interface that allows real-time trace during system debugging.
For more information about the ARM922T embedded processor, refer to the ARM922T Technical Reference Manual.
Instruction Set
All ARM9 processors and cores conform to ARM's v4T instruction set architecture, which specifies a 32-bit load-and-store instruction set that can execute every instruction conditionally. This feature allows code optimization to avoid inefficient short branches that may slow down system performance. Although the v4T 32-bit instruction set is optimized for use with 32-bit wide external memory, it can also support 16- and even 8-bit memories.
The ARM7TDMI core also uses the v4T instruction set. Any legacy software designed for an ARM7 processor core may be used in an ARM922T processor, greatly simplifying the performance upgrade path.
Figure 1 shows the ARM922T processor. For more information about the v4T instruction set, refer to the ARM® Architecture Reference Manual.
Figure 1. ARM922T Processor
Notes to Figure 1:
- JTAG = Joint Test Action Group.
- AMBA = Advanced Microcontroller Bus Architecture.
- AHB = Advanced high-performance bus.
AMBA Bus Interface & AHB
AMBA is an ARM-designed high-performance bus standard that is optimized for high-speed cache interfaces. The standard is designed to ensure that all of the ARM macrocells support a common interface for seamless connectivity. The AMBA standard supports several bus implementations: AMBA advanced high-performance bus, AMBA system bus, and AMBA peripheral bus. Excalibur devices use only the AMBA AHB standard.
Excalibur devices implement a dual AHB architecture (AHB1 and AHB2), which defines both bus masters and slaves. A bus master can initiate a bus arbiter-controlled transfer. As multiple bus masters can reside on a single AHB, the arbiter deals with multiple requests for access to the bus, prioritizing these requests when access conflicts occur. For a bus transaction, the bus master must provide address, data, and control to the bus slave it is accessing. It is possible to have a common address and data bus to reduce the interface size and, in this case, an address phase followed by a data phase for each transaction. For optimization in high-speed systems, AHB supports split transactions to aid in accessing slower peripherals, and burst transactions, which require only a starting address and a burst length to transfer multiple data items.
AHB1 is the primary system bus with the ARM922T processor as the single master shared with the on-chip single- or dual-port SRAM memories and SDRAM interface. AHB1 runs at the processor speed (up to 200 MHz), while AHB2 serves as the peripheral bus that runs at one-half the AHB frequency. AHB2 is a multi-master bus for the peripherals, the expansion bus interface (EBI) for flash memory interface, and both the master and slave AHB bridges into and from the FPGA architecture.
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