Excalibur Peripherals

UART

The UART provides a low-speed (up to 230 K Baud) serial interface between the processor and other UART-equipped devices. It also performs all necessary parallel-to-serial and serial-to-parallel conversions, and contains both receive and transmit first-in first-out (FIFO) buffers, both 16 bytes deep. A status register that monitors UART behavior may generate interrupts under certain conditions.

General-Purpose Timer

The general-purpose timer is a two-channel, 32-bit timer with a 32-bit pre-scaler. The timer may be used as a free-running (heartbeat) timer, a software-controlled interval timer with interrupt-on-limit, or a one-shot interrupt after a programmable delay. The pre-scaler is used to reduce the input clock to the timer by creating a clock-enable signal only when the pre-scaler is at its limit value.

In heartbeat mode, the timer continues to count as long as the timer start bit is set. It resets to zero automatically when it reaches its programmable limit value. An interrupt is requested (if enabled) at the end of each cycle. In interval timer mode, the status of the start bit is used under software control to start and stop the clock. An interrupt is generated (if enabled) when the timer passes through its programmable limit value. In one shot delay mode, the timer is reset to zero when the start bit is set to one, then counts in increments of one until it reaches the programmable limit value, in which the timer then generates an interrupt (if requested).

Watchdog Timer

The watchdog timer is a one-shot interval timer used to protect a system against software failures due to low power supplies or other corruption. This timer should be reset under software control periodically. If the counter expires (i.e., software does not reset the timer) the entire device is reset, putting the system back into a safe mode.

Interrupt Controller

The ARM922T^™ processor has two interrupt inputs: interrupt request (IRQ) and fast interrupt request (FIQ). Excalibur devices contain an interrupt controller that allows up to 10 interrupts from peripherals in the stripe, one external interrupt from a pin, and up to 64 interrupts from an FPGA interface. Each of six interrupt lines wired into the FPGA can function as separate IRQs, or as an interrupt bus (generating up to 64 IRQs using a separate interrupt controller in the FPGA).

All of these interrupts are maskable, have programmable priorities, and can raise either the IRQ or FIQ inputs. When an interrupt is raised, the IRQ or FIQ pin is asserted. The processor then reads the value of the registers within the interrupt controller to assess from which interrupt source it originated, to allow it to run the appropriate interrupt service routine (ISR).

The most basic of the three operating modes for the FPGA interrupt bus is the six individual interrupt sources where each interrupt is connected directly to the controller. The six bits may indicate a single interrupt request, with the priority encoded on the six data lines. Finally, a single interrupt request may be used with a five-bit priority value.

Five of the peripheral interrupts are also driven into the FPGA to allow for hardware interrupt servicing. The processor must still clear the individual interrupt flag in the interrupt controller.

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