Mercury Performance-Optimized Architecture

The Mercury^TM architecture is built for bandwidth. It offers a high-speed core that processes data at gigabit data rates and manages the clock data recovery (CDR)-generated bandwidth of 45 Gbps. The combination of high-performance features such as a high-speed prioritized interconnect, quad-port RAM capability, and distributed multiplier circuitry facilitates a high data throughput, providing an optimal solution for complex design requirements. Figure 1 shows the features of the Mercury device architecture.

Figure 1. The Mercury Architecture

Prioritized Interconnect Structure

The Mercury architecture features a prioritized interconnect structure that intelligently prioritizes signal routing to maximize performance. The prioritized interconnect structure consists of four elements (see Figure 2):

• Priority row and column lines have wider signal traces and larger line drivers, allowing for the fastest possible routing times for speed-critical signals.
• Dedicated leap lines accelerate row-to-row connections. These structures make direct connections to adjacent row lines possible and speed communication across rows, removing traditional limitations and increasing system speed.
• RapidLAB^TM interconnect provides fast connections to neighboring logic array blocks (LABs). These direct connections within a span of any ten LABs reduce the distance signals need to travel and minimize propagation delay.
• FastLUT^TM interconnect provides the fastest possible direct connection between adjacent logic elements (LEs) and enables seamless implementations of wide fan-in functions.

Figure 2. Mercury Prioritized Interconnect Structure

Mercury devices feature all-new quad-port RAM blocks in enhanced embedded system blocks (ESBs) to enable complex memory-intensive functions. The quad-port RAM allows independent access to any location within the memory block from any of its four ports, as shown in Figure 3. Quad-port RAM can be used for various data communication, storage, and telecom applications, including data concentrators, routers, frame buffer processing, multiple independent first-in first-out (FIFO) buffers, and any application requiring multiple independent clock domains.

Figure 3. Quad-Port-Capable ESB

The use of content-addressable memory (CAM) is common in many of today's high-speed communications applications. CAM accelerates fast search applications, making it ideal for packet header identification, ATM translation, and cache tagging.

Designers can partition a single Mercury ESB into two blocks, which increases the total number of memory blocks per device. Through support for quad-port RAM and CAM, as well as dual-port RAM, single-port RAM, and FIFO modes, the Mercury ESB architecture delivers flexibility for memory requirements in high-performance applications.

Distributed Multiplier Capability

Continuing Altera's commitment to DSP and wireless requirements, Mercury devices feature dedicated circuitry to implement high-speed multipliers. Mercury devices can address these applications with a dedicated multiplier mode with over 130 MHz performance for 16x16 non-pipelined multipliers. Alternatively, up to 90 separate 8x8 multipliers can be implemented in a single device. The Mercury distributed multiplier circuitry, which is automatically implemented by the Quartus^TM II software, allows the flexibility to generate smaller multipliers, ensuring that the designer can easily and efficiently implement a wide range of high-performance applications.

Related Links

Mercury Advanced CDR Support
Mercury High-Performance I/O Capabilities